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[34.126.98.232]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-74af540b394sm13073470b3a.36.2025.07.01.18.38.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jul 2025 18:38:42 -0700 (PDT) Date: Wed, 2 Jul 2025 01:38:33 +0000 From: Pranjal Shrivastava To: Nicolin Chen Cc: jgg@nvidia.com, kevin.tian@intel.com, corbet@lwn.net, will@kernel.org, bagasdotme@gmail.com, robin.murphy@arm.com, joro@8bytes.org, thierry.reding@gmail.com, vdumpa@nvidia.com, jonathanh@nvidia.com, shuah@kernel.org, jsnitsel@redhat.com, nathan@kernel.org, peterz@infradead.org, yi.l.liu@intel.com, mshavit@google.com, zhangzekun11@huawei.com, iommu@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org, linux-kselftest@vger.kernel.org, patches@lists.linux.dev, mochs@nvidia.com, alok.a.tiwari@oracle.com, vasant.hegde@amd.com, dwmw2@infradead.org, baolu.lu@linux.intel.com Subject: Re: [PATCH v7 27/28] iommu/tegra241-cmdqv: Add user-space use support Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250701_183844_067967_02A37653 X-CRM114-Status: GOOD ( 30.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jul 01, 2025 at 05:46:06PM -0700, Nicolin Chen wrote: > On Wed, Jul 02, 2025 at 12:14:28AM +0000, Pranjal Shrivastava wrote: > > Thus, coming back to the two initial points: > > > > 1) Issuing "non-invalidation" commands through .cache_invalidate could > > be confusing, I'm not asking to change the op name here, but if we > > plan to label it, let's label them as "Trapped commands" OR > > "non-accelerated" commands as you suggested. > > VCMDQ only accelerates limited invalidation commands, not all of > them: STE cache invalidation and CD cache invalidation commands > still go down to that op. > Right, I'm just saying the "other" non-accelerated commands that are NOT invalidations also go down that op. So, if we add a comment, let's not call them "non-invalidation" commands. > > 2) The "FIXME" confusion: The comment in arm_vsmmu_cache_invalidate > > mentions we'd like to "fix" the issuing of commands through the main > > cmdq and instead like to group by "type", if that "type" is the queue > > type (which I assume it is because IOMMU_TYPE has to be arm-smmu-v3), > > I recall that FIXME is noted by Jason at that time. And it should > be interpreted as "group by opcode", IIUIC. I see.. I misunderstood that.. > > The thing is that for a host kernel that enabled in-kernel VCMDQs, > those trapped user commands can be just issued to the smmu->cmdq > or a vcmdq (picked via the get_secondary_cmdq impl_op). > Ohh.. so maybe some sort of a load balancing thing? > > what do we plan to do differently there, given that the op is only > > for trapped commands *have* to go through the main CMDQ? > > If we do something differently there, it could just do a one-time > get_secondary_cmdq call to pick a in-kernel vcmdq over smmu->cmdq > to fill in all the trapped commands. > Alright. > And this is not related to this series at all. Agreed, sorry for the confusion then.. I thought that the "type" meant the queue type.. I guess it's all done then. I have no further questions Thanks for the clarification! > > Nicolin Praan