From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 31D67C83030 for ; Thu, 3 Jul 2025 20:59:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=cbsa/0objYW1VIF1CBCBG2w7EsI/vr7EijqMyJxiWZE=; b=L8kulvK50yYCHLnHHVHIGegKFg VN5PGs5UaTRI9Ng3T60qDtFrqPBvUh7egyp9QZoxDiHtudEf8AbgH+pf3EvrVVbnD8L1F/1Vgovpk zAVDYav+dQ+Q52oEsR7mid2TxR3GqCfjj+9pUrzHAM8hUq+cap6Nbq6QuMsZAwb6qZ9UUWTNFL5i4 Gz4VkLhk4rjALIkr9MjfhOyueHac1gwserC/7QeExRTPCfRMIejmijaVHOnaSDDxVARAECa+TciLZ VPlIpTHZB2e7ywfe9AsjY/dRVfjdA1iaTbCPWtVYeDZLTIIldfiGmNagzmGbfGrm4HMIO8R8tPx8w vn3b4OnQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uXR1s-0000000CWo8-3lJm; Thu, 03 Jul 2025 20:59:36 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uXMSr-0000000BwMt-3cEM for linux-arm-kernel@lists.infradead.org; Thu, 03 Jul 2025 16:07:11 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 4ACB35C662E; Thu, 3 Jul 2025 16:07:09 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9A8C3C4CEE3; Thu, 3 Jul 2025 16:07:05 +0000 (UTC) Date: Thu, 3 Jul 2025 17:07:03 +0100 From: Catalin Marinas To: Lorenzo Pieralisi Cc: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Will Deacon , Arnd Bergmann , Sascha Bischoff , Jonathan Cameron , Timothy Hayes , Bjorn Helgaas , "Liam R. Howlett" , Peter Maydell , Mark Rutland , Jiri Slaby , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v7 21/31] irqchip/gic-v5: Add GICv5 IRS/SPI support Message-ID: References: <20250703-gicv5-host-v7-0-12e71f1b3528@kernel.org> <20250703-gicv5-host-v7-21-12e71f1b3528@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250703-gicv5-host-v7-21-12e71f1b3528@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250703_090709_944516_FEC67FC2 X-CRM114-Status: GOOD ( 21.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jul 03, 2025 at 12:25:11PM +0200, Lorenzo Pieralisi wrote: > The GICv5 Interrupt Routing Service (IRS) component implements > interrupt management and routing in the GICv5 architecture. > > A GICv5 system comprises one or more IRSes, that together > handle the interrupt routing and state for the system. > > An IRS supports Shared Peripheral Interrupts (SPIs), that are > interrupt sources directly connected to the IRS; they do not > rely on memory for storage. The number of supported SPIs is > fixed for a given implementation and can be probed through IRS > IDR registers. > > SPI interrupt state and routing are managed through GICv5 > instructions. > > Each core (PE in GICv5 terms) in a GICv5 system is identified with > an Interrupt AFFinity ID (IAFFID). > > An IRS manages a set of cores that are connected to it. > > Firmware provides a topology description that the driver uses > to detect to which IRS a CPU (ie an IAFFID) is associated with. > > Use probeable information and firmware description to initialize > the IRSes and implement GICv5 IRS SPIs support through an > SPI-specific IRQ domain. > > The GICv5 IRS driver: > > - Probes IRSes in the system to detect SPI ranges > - Associates an IRS with a set of cores connected to it > - Adds an IRQchip structure for SPI handling > > SPIs priority is set to a value corresponding to the lowest > permissible priority in the system (taking into account the > implemented priority bits of the IRS and CPU interface). > > Since all IRQs are set to the same priority value, the value > itself does not matter as long as it is a valid one. > > Co-developed-by: Sascha Bischoff > Signed-off-by: Sascha Bischoff > Co-developed-by: Timothy Hayes > Signed-off-by: Timothy Hayes > Signed-off-by: Lorenzo Pieralisi > Reviewed-by: Marc Zyngier > Cc: Will Deacon > Cc: Thomas Gleixner > Cc: Catalin Marinas > Cc: Marc Zyngier Acked-by: Catalin Marinas