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Mon, 21 Jul 2025 07:52:19 -0700 (PDT) Received: from geday ([2804:7f2:800b:6584::dead:c001]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-53764f2bd69sm2823702e0c.14.2025.07.21.07.52.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Jul 2025 07:52:18 -0700 (PDT) Date: Mon, 21 Jul 2025 11:52:12 -0300 From: Geraldo Nascimento To: Robin Murphy Cc: linux-rockchip@lists.infradead.org, Neil Armstrong , Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Rick wertenbroek , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v7 3/4] phy: rockchip-pcie: Enable all four lanes if required Message-ID: References: <2affed16-f3c4-47d3-9ca6-e4f48e875367@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2affed16-f3c4-47d3-9ca6-e4f48e875367@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250721_075221_088300_87D34E99 X-CRM114-Status: GOOD ( 14.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jun 30, 2025 at 02:48:25PM +0100, Robin Murphy wrote: > On 29/06/2025 9:58 pm, Geraldo Nascimento wrote: > > Current code enables only Lane 0 because pwr_cnt will be incremented on > > first call to the function. Let's reorder the enablement code to enable > > all 4 lanes through GRF. > > As usual the TRM isn't very clear, but the way it describes the > GRF_SOC_CON_5_PCIE bits does suggest they're driving external input > signals of the phy block, so it seems reasonable that it could be OK to > update the register itself without worrying about releasing the phy from > reset first. In that case I'd agree this seems the cleanest fix, and if > it works empirically then I think I'm now sufficiently convinced too; > > Reviewed-by: Robin Murphy Hi everyone, Patches 1 and 2 of this series were merged thhrough pci git but patches 3 and 4 of present series got R-b's but were completely ignored by phy maintainers. Do you think it's fair if I resend these ones with a new, phy only, cover letter but keep the R-b tags? Thank you, Geraldo Nascimento