From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5F27C83F1A for ; Mon, 14 Jul 2025 13:33:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=EAkoISUbiC467XwET00w80/uJPEa5DP4wPMhGYodO/4=; b=LzyvMnfApS2qQY+eLIOazt6xK3 fu8FAf1WMzU2swSqFuDqc2nBat3LrShz74ypoVfQLkJFlT695K5XznCIGY24TUcmfn0HM2cWZjekj SnBIFSTncil65SI4haN7Qs8SAkYYzRRnUWgd2F/QI4iX1HpzFkwXrtEgLehfTtBEbN7Zm5DNJ0YGQ Jz1hqeztMYFW1rAkCIh3H4wBhXDjN1I3vb4ZPIYgXVBXDugkwCeHANHjc+tCPROtUuhISiWEpO248 gwyrZNYKlu0wDgzVN33uhCHEc9QfYqH2JUHfwBq2HrCPHiBS5rNBHvII7UEoGQud6KIdwV8ItuEFr RCLNv4Tw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1ubJIk-00000002JKw-43jV; Mon, 14 Jul 2025 13:33:02 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1ubJCh-00000002Hx4-4Aj5 for linux-arm-kernel@lists.infradead.org; Mon, 14 Jul 2025 13:26:49 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 4FAE25C43B5; Mon, 14 Jul 2025 13:26:47 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0F583C4CEED; Mon, 14 Jul 2025 13:26:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1752499607; bh=F0h9qPfS1IFEzVFRGzECq3FkHstZL9RWV6sL0z924sM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=qw1miNrNBh0wkTZ/anfy7aGB7/NfB3gC2jbI1iY9RGdvO/jyibOW8mHgITKi/WHqR 9oruhqtRVHi/HQFfXtVrXuYJ8tZSUnO4DVdS2NHst28qKNxNDDzU6WK5nYKhHQJYVb uowtKbBVr9JRIUntIH7+S1lUBzaDpxa9otPil7K44hjlPzCqul67n3QFd3ZGZczViR U+QDSKRGKRyVd5PIhDK8FPKGWsmsA9XaPAHHpeTvU5IVhI4905xdRra3VdM/HwM3UG KBpN/xFSGxOEZpAnqx2ouiyPiaYCl3uVQthDvJqmqbutytAYTgehiKk7kY17tExVdO uzSg3fUKz4cAA== Date: Mon, 14 Jul 2025 14:26:39 +0100 From: Will Deacon To: James Clark Cc: Catalin Marinas , Mark Rutland , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , leo.yan@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev Subject: Re: [PATCH v3 02/10] perf: arm_spe: Support FEAT_SPEv1p4 filters Message-ID: References: <20250605-james-perf-feat_spe_eft-v3-0-71b0c9f98093@linaro.org> <20250605-james-perf-feat_spe_eft-v3-2-71b0c9f98093@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250605-james-perf-feat_spe_eft-v3-2-71b0c9f98093@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250714_062648_115938_9B8E822F X-CRM114-Status: GOOD ( 21.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jun 05, 2025 at 11:49:00AM +0100, James Clark wrote: > FEAT_SPEv1p4 (optional from Armv8.8) adds some new filter bits, so > remove them from the previous version's RES0 bits using > PMSEVFR_EL1_RES0_V1P4_EXCL. It also makes some previously available bits > unavailable again, so add those back using PMSEVFR_EL1_RES0_V1P4_INCL. > E.g: > > E[30], bit [30] > When FEAT_SPEv1p4 is _not_ implemented ... > > FEAT_SPE_V1P3 has the same filters as V1P2 so explicitly add it to the > switch. > > Reviewed-by: Leo Yan > Tested-by: Leo Yan > Signed-off-by: James Clark > --- > arch/arm64/include/asm/sysreg.h | 7 +++++++ > drivers/perf/arm_spe_pmu.c | 5 ++++- > 2 files changed, 11 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index f1bb0d10c39a..880090df3efc 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -358,6 +358,13 @@ > (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) > #define PMSEVFR_EL1_RES0_V1P2 \ > (PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6)) > +#define PMSEVFR_EL1_RES0_V1P4_EXCL \ > + (BIT_ULL(2) | BIT_ULL(4) | GENMASK_ULL(10, 8) | GENMASK_ULL(23, 19)) > +#define PMSEVFR_EL1_RES0_V1P4_INCL \ > + (GENMASK_ULL(31, 26)) > +#define PMSEVFR_EL1_RES0_V1P4 \ > + (PMSEVFR_EL1_RES0_V1P4_INCL | \ > + (PMSEVFR_EL1_RES0_V1P2 & ~PMSEVFR_EL1_RES0_V1P4_EXCL)) > > /* Buffer error reporting */ > #define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT > diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c > index 3efed8839a4e..d9f6d229dce8 100644 > --- a/drivers/perf/arm_spe_pmu.c > +++ b/drivers/perf/arm_spe_pmu.c > @@ -701,9 +701,12 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver) > case ID_AA64DFR0_EL1_PMSVer_V1P1: > return PMSEVFR_EL1_RES0_V1P1; > case ID_AA64DFR0_EL1_PMSVer_V1P2: > + case ID_AA64DFR0_EL1_PMSVer_V1P3: > + return PMSEVFR_EL1_RES0_V1P2; > + case ID_AA64DFR0_EL1_PMSVer_V1P4: > /* Return the highest version we support in default */ > default: > - return PMSEVFR_EL1_RES0_V1P2; > + return PMSEVFR_EL1_RES0_V1P4; See my reply [1] to Leo about this function, but I think we should just remove it. Will [1] https://lore.kernel.org/all/20250707-arm_spe_support_hitm_overhead_v1_public-v3-0-33ea82da3280@arm.com/