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charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250718_033957_960345_996654B5 X-CRM114-Status: GOOD ( 13.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jul 18, 2025 at 12:28:44PM +0200, Niklas Cassel wrote: > On Tue, Jul 15, 2025 at 07:51:03PM +0530, Manivannan Sadhasivam via B4 Relay wrote: > 2) Testing link down reset: > > selftests before link down reset: > # FAILED: 14 / 16 tests passed. > > ## On EP side: > # echo 0 > /sys/kernel/config/pci_ep/controllers/a40000000.pcie-ep/start && \ > sleep 0.1 && echo 1 > /sys/kernel/config/pci_ep/controllers/a40000000.pcie-ep/start > > > [ 111.137162] rockchip-dw-pcie a40000000.pcie: PCIE_CLIENT_INTR_STATUS_MISC: 0x4 > [ 111.137881] rockchip-dw-pcie a40000000.pcie: LTSSM_STATUS: 0x0 > [ 111.138432] rockchip-dw-pcie a40000000.pcie: hot reset or link-down reset > [ 111.139067] pcieport 0000:00:00.0: Recovering Root Port due to Link Down > [ 111.139686] pci-endpoint-test 0000:01:00.0: AER: can't recover (no error_detected callback) > [ 111.255407] rockchip-dw-pcie a40000000.pcie: PCIe Gen.3 x4 link up > [ 111.256019] rockchip-dw-pcie a40000000.pcie: Root Port reset completed > [ 111.383401] pcieport 0000:00:00.0: Root Port has been reset > [ 111.384060] pcieport 0000:00:00.0: AER: device recovery failed > [ 111.384582] rockchip-dw-pcie a40000000.pcie: PCIE_CLIENT_INTR_STATUS_MISC: 0x3 > [ 111.385218] rockchip-dw-pcie a40000000.pcie: LTSSM_STATUS: 0x230011 > [ 111.385771] rockchip-dw-pcie a40000000.pcie: Received Link up event. Starting enumeration! > [ 111.390866] pcieport 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring > [ 111.391650] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01 > > Basically all tests timeout > # FAILED: 1 / 16 tests passed. > > Which is the same as before this patch series. The above was with CONFIG_PCIEAER=y Wilfred suggested that I tried without this config set. However, doing so, I got the exact same result: # FAILED: 1 / 16 tests passed. For the record, the test that passes is not actually passing either, it is the BAR4 test, which is skipped, since BAR4 is reserved on rock5b: ok 5 pci_ep_bar.BAR4.BAR_TEST # SKIP BAR is disabled Kind regards, Niklas