From: Mark Rutland <mark.rutland@arm.com>
To: Yicong Yang <yangyicong@huawei.com>
Cc: James Clark <james.clark@linaro.org>,
will@kernel.org, linux-arm-kernel@lists.infradead.org,
yangyicong@hisilicon.com, robh@kernel.org,
anshuman.khandual@arm.com, jonathan.cameron@huawei.com,
hejunhao3@huawei.com, linuxarm@huawei.com,
prime.zeng@hisilicon.com, xuwei5@huawei.com,
wangyushan12@huawei.com
Subject: Re: [PATCH 2/2] perf: arm_pmuv3: Don't use PMCCNTR_EL0 on SMT cores
Date: Tue, 12 Aug 2025 11:22:38 +0100 [thread overview]
Message-ID: <aJsV7nzlILHd_ZMa@J2N7QTR9R3> (raw)
In-Reply-To: <931e26ef-bdc6-5f9e-8976-d5a4b8e6e81f@huawei.com>
On Tue, Aug 12, 2025 at 06:14:33PM +0800, Yicong Yang wrote:
> On 2025/8/12 18:00, James Clark wrote:
> > On 12/08/2025 9:08 am, Yicong Yang wrote:
> >> @@ -1002,6 +1002,15 @@ static bool armv8pmu_can_use_pmccntr(struct pmu_hw_events *cpuc,
> >> if (has_branch_stack(event))
> >> return false;
> >> + /*
> >> + * The PMCCNTR_EL0 increments from the processor clock rather than
> >> + * the PE clock (ARM DDI0487 L.b D13.1.3) which means it'll continue
> >> + * counting on a WFI PE if one of its SMT silbing is not idle on a
> >> + * multi-threaded implementation. So don't use it on SMT cores.
> >> + */
> >> + if (cpumask_weight(topology_sibling_cpumask(smp_processor_id())) > 1)
> >> + return false;
> >> +
> >
> > Isn't this something that's static to the PMU? If all CPUs in each PMU are always the same then this doesn't need to be probed every time and can be set once.
> >
> we can make use of PMCCNTR_EL0 if the SMT is runtime disabled, e.g. by /sys/devices/system/cpu/smt/control
> if set this at probe time then we permanently lose the chance to use PMCCNTR_EL0.
Can it be runtime enabled too?
If so, then we can't use PMCCNTR_EL0 in case we later dynamically go
from disabled to enabled.
I do not think this should be handled dynamically.
> > Also you can't call smp_processor_id() from here because this is
> > also called in armpmu_event_init() -> __hw_perf_event_init() ->
> > validate_group() before the event is actually scheduled on a CPU.
> > With CONFIG_DEBUG_PREEMPT you'd see the error.
>
> ok, will use raw_smp_processor_id() instead. it won't affect the validation checking in pmu::event_init().
> in pmu::add() the cpu id is always stable so it'll also be fine.
NAK to this.
It *will* affect validation since it affects the number of events that
can be placed into a single group (by virtue of allowing or forbidding
an additional cycles events). That would be non-deterministic, which is
horrible to debug.
Mark.
next prev parent reply other threads:[~2025-08-12 16:19 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-12 8:08 [PATCH 0/2] perf: arm_pmuv3: Don't use PMCCNTR_EL0 on SMT cores Yicong Yang
2025-08-12 8:08 ` [PATCH 1/2] perf: arm_pmuv3: Factor out PMCCNTR_EL0 use conditions Yicong Yang
2025-08-12 10:02 ` James Clark
2025-08-12 10:25 ` Mark Rutland
2025-08-12 8:08 ` [PATCH 2/2] perf: arm_pmuv3: Don't use PMCCNTR_EL0 on SMT cores Yicong Yang
2025-08-12 10:00 ` James Clark
2025-08-12 10:14 ` Yicong Yang
2025-08-12 10:22 ` Mark Rutland [this message]
2025-08-13 8:17 ` Yicong Yang
2025-08-12 10:31 ` James Clark
2025-08-13 8:32 ` Yicong Yang
2025-08-12 10:33 ` Mark Rutland
2025-08-13 8:03 ` Yicong Yang
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