From: Dave Martin <Dave.Martin@arm.com>
To: James Morse <james.morse@arm.com>
Cc: linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org,
devicetree@vger.kernel.org, shameerali.kolothum.thodi@huawei.com,
D Scott Phillips OS <scott@os.amperecomputing.com>,
carl@os.amperecomputing.com, lcherian@marvell.com,
bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com,
baolin.wang@linux.alibaba.com,
Jamie Iles <quic_jiles@quicinc.com>,
Xin Hao <xhao@linux.alibaba.com>,
peternewman@google.com, dfustini@baylibre.com,
amitsinght@marvell.com, David Hildenbrand <david@redhat.com>,
Rex Nie <rex.nie@jaguarmicro.com>, Koba Ko <kobak@nvidia.com>,
Shanker Donthineni <sdonthineni@nvidia.com>,
fenghuay@nvidia.com, baisheng.gao@unisoc.com,
Jonathan Cameron <jonathan.cameron@huawei.com>,
Rob Herring <robh@kernel.org>,
Rohit Mathew <rohit.mathew@arm.com>,
Rafael Wysocki <rafael@kernel.org>, Len Brown <lenb@kernel.org>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
Hanjun Guo <guohanjun@huawei.com>,
Sudeep Holla <sudeep.holla@arm.com>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Danilo Krummrich <dakr@kernel.org>
Subject: Re: [PATCH 05/33] ACPI / PPTT: Find cache level by cache-id
Date: Wed, 27 Aug 2025 11:50:56 +0100 [thread overview]
Message-ID: <aK7jEMqM/FoB4ABW@e133380.arm.com> (raw)
In-Reply-To: <20250822153048.2287-6-james.morse@arm.com>
Hi,
On Fri, Aug 22, 2025 at 03:29:46PM +0000, James Morse wrote:
> The MPAM table identifies caches by id. The MPAM driver also wants to know
> the cache level to determine if the platform is of the shape that can be
> managed via resctrl. Cacheinfo has this information, but only for CPUs that
> are online.
>
> Waiting for all CPUs to come online is a problem for platforms where
> CPUs are brought online late by user-space.
>
> Add a helper that walks every possible cache, until it finds the one
> identified by cache-id, then return the level.
> Add a cleanup based free-ing mechanism for acpi_get_table().
Does this mean that the early secondaries must be spread out across the
whole topology so that everything can be probed?
(i.e., a random subset is no good?)
If so, is this documented somewhere, such as in booting.rst?
Maybe this is not a new requirement -- it's not an area that I'm very
familiar with.
>
> CC: Jonathan Cameron <jonathan.cameron@huawei.com>
> Signed-off-by: James Morse <james.morse@arm.com>
> ---
> Changes since RFC:
> * acpi_count_levels() now returns a value.
> * Converted the table-get stuff to use Jonathan's cleanup helper.
> * Dropped Sudeep's Review tag due to the cleanup change.
> ---
> drivers/acpi/pptt.c | 64 ++++++++++++++++++++++++++++++++++++++++++++
> include/linux/acpi.h | 17 ++++++++++++
> 2 files changed, 81 insertions(+)
>
> diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c
> index 8f9b9508acba..660457644a5b 100644
> --- a/drivers/acpi/pptt.c
> +++ b/drivers/acpi/pptt.c
> @@ -907,3 +907,67 @@ int find_acpi_cpu_topology_hetero_id(unsigned int cpu)
> return find_acpi_cpu_topology_tag(cpu, PPTT_ABORT_PACKAGE,
> ACPI_PPTT_ACPI_IDENTICAL);
> }
> +
> +/**
> + * find_acpi_cache_level_from_id() - Get the level of the specified cache
> + * @cache_id: The id field of the unified cache
> + *
> + * Determine the level relative to any CPU for the unified cache identified by
> + * cache_id. This allows the property to be found even if the CPUs are offline.
> + *
> + * The returned level can be used to group unified caches that are peers.
> + *
> + * The PPTT table must be rev 3 or later,
> + *
> + * If one CPUs L2 is shared with another as L3, this function will return
> + * an unpredictable value.
> + *
> + * Return: -ENOENT if the PPTT doesn't exist, or the cache cannot be found.
Nit: doesn't exist or its revision is too old.
> + * Otherwise returns a value which represents the level of the specified cache.
> + */
> +int find_acpi_cache_level_from_id(u32 cache_id)
> +{
> + u32 acpi_cpu_id;
> + int level, cpu, num_levels;
> + struct acpi_pptt_cache *cache;
> + struct acpi_pptt_cache_v1 *cache_v1;
> + struct acpi_pptt_processor *cpu_node;
> + struct acpi_table_header *table __free(acpi_table) = acpi_get_table_ret(ACPI_SIG_PPTT, 0);
acpi_get_pptt() ? (See comment on patch 3.)
Comments there also suggest that the acpi_put_table() may be
unnecessary, at least on some paths.
I haven't tried to understand the ins and outs of this.
> +
> + if (IS_ERR(table))
> + return PTR_ERR(table);
> +
> + if (table->revision < 3)
> + return -ENOENT;
> +
> + /*
> + * If we found the cache first, we'd still need to walk from each CPU
> + * to find the level...
> + */
^ Possibly confusing comment? The cache id is the starting point for
calling this function. Is there a world in which we are at this point
without first having found the cache node?
(If the comment is just a restatement of part of the kerneldoc
description, maybe just drop it.)
> + for_each_possible_cpu(cpu) {
> + acpi_cpu_id = get_acpi_id_for_cpu(cpu);
> + cpu_node = acpi_find_processor_node(table, acpi_cpu_id);
> + if (!cpu_node)
> + return -ENOENT;
> + num_levels = acpi_count_levels(table, cpu_node, NULL);
Is the initial call to acpi_count_levels() really needed here?
It feels a bit like we end up enumerating the whole topology two or
three times here; once to count how many levels there are, and then
again to examine the nodes, and once more inside acpi_find_cache_node().
Why can't we just walk until we run out of levels?
I may be missing some details of how these functions interact -- if
this is only run at probe time, compact, well-factored code is
more important than making things as fast as possible.
> +
> + /* Start at 1 for L1 */
> + for (level = 1; level <= num_levels; level++) {
> + cache = acpi_find_cache_node(table, acpi_cpu_id,
> + ACPI_PPTT_CACHE_TYPE_UNIFIED,
> + level, &cpu_node);
> + if (!cache)
> + continue;
> +
> + cache_v1 = ACPI_ADD_PTR(struct acpi_pptt_cache_v1,
> + cache,
> + sizeof(struct acpi_pptt_cache));
> +
> + if (cache->flags & ACPI_PPTT_CACHE_ID_VALID &&
> + cache_v1->cache_id == cache_id)
> + return level;
> + }
> + }
> +
> + return -ENOENT;
> +}
> diff --git a/include/linux/acpi.h b/include/linux/acpi.h
> index f97a9ff678cc..30c10b1dcdb2 100644
> --- a/include/linux/acpi.h
> +++ b/include/linux/acpi.h
[...]
> @@ -221,6 +222,17 @@ void acpi_reserve_initial_tables (void);
> void acpi_table_init_complete (void);
> int acpi_table_init (void);
>
> +static inline struct acpi_table_header *acpi_get_table_ret(char *signature, u32 instance)
> +{
> + struct acpi_table_header *table;
> + int status = acpi_get_table(signature, instance, &table);
> +
> + if (ACPI_FAILURE(status))
> + return ERR_PTR(-ENOENT);
> + return table;
> +}
This feels like something that ought to exist already. If not, why
not? If so, are there open-coded versions of this spread around the
ACPI tree that should be ported to use it?
[...]
Cheers
---Dave
next prev parent reply other threads:[~2025-08-27 11:37 UTC|newest]
Thread overview: 130+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-22 15:29 [PATCH 00/33] arm_mpam: Add basic mpam driver James Morse
2025-08-22 15:29 ` [PATCH 01/33] cacheinfo: Expose the code to generate a cache-id from a device_node James Morse
2025-08-27 10:46 ` Dave Martin
2025-08-27 17:11 ` James Morse
2025-08-28 14:08 ` Dave Martin
2025-08-22 15:29 ` [PATCH 02/33] drivers: base: cacheinfo: Add helper to find the cache size from cpu+level James Morse
2025-08-24 17:25 ` Krzysztof Kozlowski
2025-08-27 17:11 ` James Morse
2025-08-27 10:46 ` Dave Martin
2025-08-27 17:11 ` James Morse
2025-08-28 14:10 ` Dave Martin
2025-08-22 15:29 ` [PATCH 03/33] ACPI / PPTT: Add a helper to fill a cpumask from a processor container James Morse
2025-08-26 14:45 ` Ben Horgan
2025-08-28 15:56 ` James Morse
2025-08-27 10:48 ` Dave Martin
2025-08-28 15:57 ` James Morse
2025-08-22 15:29 ` [PATCH 04/33] ACPI / PPTT: Stop acpi_count_levels() expecting callers to clear levels James Morse
2025-08-27 10:49 ` Dave Martin
2025-08-28 15:57 ` James Morse
2025-08-22 15:29 ` [PATCH 05/33] ACPI / PPTT: Find cache level by cache-id James Morse
2025-08-23 12:14 ` Markus Elfring
2025-08-28 15:57 ` James Morse
2025-08-27 9:25 ` Ben Horgan
2025-08-28 15:57 ` James Morse
2025-08-27 10:50 ` Dave Martin [this message]
2025-08-28 15:58 ` James Morse
2025-08-22 15:29 ` [PATCH 06/33] ACPI / PPTT: Add a helper to fill a cpumask from a cache_id James Morse
2025-08-27 10:53 ` Dave Martin
2025-08-28 15:58 ` James Morse
2025-08-22 15:29 ` [PATCH 07/33] arm64: kconfig: Add Kconfig entry for MPAM James Morse
2025-08-27 8:53 ` Ben Horgan
2025-08-28 15:58 ` James Morse
2025-08-29 8:20 ` Ben Horgan
2025-08-27 11:01 ` Dave Martin
2025-08-22 15:29 ` [PATCH 08/33] ACPI / MPAM: Parse the MPAM table James Morse
2025-08-23 10:55 ` Markus Elfring
2025-08-27 16:05 ` Dave Martin
2025-08-22 15:29 ` [PATCH 09/33] dt-bindings: arm: Add MPAM MSC binding James Morse
2025-08-27 16:22 ` Dave Martin
2025-08-22 15:29 ` [PATCH 10/33] arm_mpam: Add probe/remove for mpam msc driver and kbuild boiler plate James Morse
2025-08-22 19:15 ` Markus Elfring
2025-08-22 19:55 ` Markus Elfring
2025-08-23 6:41 ` Greg Kroah-Hartman
2025-08-27 13:03 ` Ben Horgan
2025-08-27 15:39 ` Rob Herring
2025-08-27 16:16 ` Rob Herring
2025-09-01 9:11 ` Ben Horgan
2025-09-01 11:21 ` Dave Martin
2025-08-22 15:29 ` [PATCH 11/33] arm_mpam: Add support for memory controller MSC on DT platforms James Morse
2025-08-22 15:29 ` [PATCH 12/33] arm_mpam: Add the class and component structures for ris firmware described James Morse
2025-08-28 1:29 ` Fenghua Yu
2025-09-01 11:09 ` Dave Martin
2025-08-22 15:29 ` [PATCH 13/33] arm_mpam: Add MPAM MSC register layout definitions James Morse
2025-08-29 8:42 ` Ben Horgan
2025-08-22 15:29 ` [PATCH 14/33] arm_mpam: Add cpuhp callbacks to probe MSC hardware James Morse
2025-08-27 16:08 ` Rob Herring
2025-08-22 15:29 ` [PATCH 15/33] arm_mpam: Probe MSCs to find the supported partid/pmg values James Morse
2025-08-28 13:12 ` Ben Horgan
2025-08-22 15:29 ` [PATCH 16/33] arm_mpam: Add helpers for managing the locking around the mon_sel registers James Morse
2025-08-28 17:07 ` Fenghua Yu
2025-08-22 15:29 ` [PATCH 17/33] arm_mpam: Probe the hardware features resctrl supports James Morse
2025-08-28 13:44 ` Ben Horgan
2025-08-22 15:29 ` [PATCH 18/33] arm_mpam: Merge supported features during mpam_enable() into mpam_class James Morse
2025-08-29 13:54 ` Ben Horgan
2025-08-22 15:30 ` [PATCH 19/33] arm_mpam: Reset MSC controls from cpu hp callbacks James Morse
2025-08-27 16:19 ` Ben Horgan
2025-08-22 15:30 ` [PATCH 20/33] arm_mpam: Add a helper to touch an MSC from any CPU James Morse
2025-08-28 16:13 ` Ben Horgan
2025-08-22 15:30 ` [PATCH 21/33] arm_mpam: Extend reset logic to allow devices to be reset any time James Morse
2025-08-29 14:30 ` Ben Horgan
2025-08-22 15:30 ` [PATCH 22/33] arm_mpam: Register and enable IRQs James Morse
2025-08-22 15:30 ` [PATCH 23/33] arm_mpam: Use a static key to indicate when mpam is enabled James Morse
2025-08-22 15:30 ` [PATCH 24/33] arm_mpam: Allow configuration to be applied and restored during cpu online James Morse
2025-08-28 16:13 ` Ben Horgan
2025-08-22 15:30 ` [PATCH 25/33] arm_mpam: Probe and reset the rest of the features James Morse
2025-08-28 10:11 ` Ben Horgan
2025-08-22 15:30 ` [PATCH 26/33] arm_mpam: Add helpers to allocate monitors James Morse
2025-08-29 15:47 ` Ben Horgan
2025-08-22 15:30 ` [PATCH 27/33] arm_mpam: Add mpam_msmon_read() to read monitor value James Morse
2025-08-29 15:55 ` Ben Horgan
2025-08-22 15:30 ` [PATCH 28/33] arm_mpam: Track bandwidth counter state for overflow and power management James Morse
2025-08-29 16:09 ` Ben Horgan
2025-08-22 15:30 ` [PATCH 29/33] arm_mpam: Probe for long/lwd mbwu counters James Morse
2025-08-28 16:14 ` Ben Horgan
2025-08-22 15:30 ` [PATCH 30/33] arm_mpam: Use long MBWU counters if supported James Morse
2025-08-29 16:39 ` Ben Horgan
2025-08-22 15:30 ` [PATCH 31/33] arm_mpam: Add helper to reset saved mbwu state James Morse
2025-08-22 15:30 ` [PATCH 32/33] arm_mpam: Add kunit test for bitmap reset James Morse
2025-08-29 16:56 ` Ben Horgan
2025-08-22 15:30 ` [PATCH 33/33] arm_mpam: Add kunit tests for props_mismatch() James Morse
2025-08-29 17:11 ` Ben Horgan
2025-08-22 15:30 ` [PATCH 00/33] arm_mpam: Add basic mpam driver James Morse
2025-08-22 15:30 ` [PATCH 01/33] cacheinfo: Expose the code to generate a cache-id from a device_node James Morse
2025-08-22 15:30 ` [PATCH 02/33] drivers: base: cacheinfo: Add helper to find the cache size from cpu+level James Morse
2025-08-22 15:30 ` [PATCH 03/33] ACPI / PPTT: Add a helper to fill a cpumask from a processor container James Morse
2025-08-22 15:30 ` [PATCH 04/33] ACPI / PPTT: Stop acpi_count_levels() expecting callers to clear levels James Morse
2025-08-22 15:30 ` [PATCH 05/33] ACPI / PPTT: Find cache level by cache-id James Morse
2025-08-22 15:30 ` [PATCH 06/33] ACPI / PPTT: Add a helper to fill a cpumask from a cache_id James Morse
2025-08-22 15:30 ` [PATCH 07/33] arm64: kconfig: Add Kconfig entry for MPAM James Morse
2025-08-22 15:30 ` [PATCH 08/33] ACPI / MPAM: Parse the MPAM table James Morse
2025-08-22 15:30 ` [PATCH 09/33] dt-bindings: arm: Add MPAM MSC binding James Morse
2025-08-22 15:30 ` [PATCH 10/33] arm_mpam: Add probe/remove for mpam msc driver and kbuild boiler plate James Morse
2025-08-22 15:30 ` [PATCH 11/33] arm_mpam: Add support for memory controller MSC on DT platforms James Morse
2025-08-22 15:30 ` [PATCH 12/33] arm_mpam: Add the class and component structures for ris firmware described James Morse
2025-08-29 12:41 ` Ben Horgan
2025-08-22 15:30 ` [PATCH 13/33] arm_mpam: Add MPAM MSC register layout definitions James Morse
2025-08-22 15:30 ` [PATCH 14/33] arm_mpam: Add cpuhp callbacks to probe MSC hardware James Morse
2025-08-22 15:30 ` [PATCH 15/33] arm_mpam: Probe MSCs to find the supported partid/pmg values James Morse
2025-08-22 15:30 ` [PATCH 16/33] arm_mpam: Add helpers for managing the locking around the mon_sel registers James Morse
2025-08-22 15:30 ` [PATCH 17/33] arm_mpam: Probe the hardware features resctrl supports James Morse
2025-08-22 15:30 ` [PATCH 18/33] arm_mpam: Merge supported features during mpam_enable() into mpam_class James Morse
2025-08-22 15:30 ` [PATCH 19/33] arm_mpam: Reset MSC controls from cpu hp callbacks James Morse
2025-08-22 15:30 ` [PATCH 20/33] arm_mpam: Add a helper to touch an MSC from any CPU James Morse
2025-08-22 15:30 ` [PATCH 21/33] arm_mpam: Extend reset logic to allow devices to be reset any time James Morse
2025-08-22 15:30 ` [PATCH 22/33] arm_mpam: Register and enable IRQs James Morse
2025-09-01 10:05 ` Ben Horgan
2025-08-22 15:30 ` [PATCH 23/33] arm_mpam: Use a static key to indicate when mpam is enabled James Morse
2025-08-22 15:30 ` [PATCH 24/33] arm_mpam: Allow configuration to be applied and restored during cpu online James Morse
2025-08-22 15:30 ` [PATCH 25/33] arm_mpam: Probe and reset the rest of the features James Morse
2025-08-22 15:30 ` [PATCH 26/33] arm_mpam: Add helpers to allocate monitors James Morse
2025-08-22 15:30 ` [PATCH 27/33] arm_mpam: Add mpam_msmon_read() to read monitor value James Morse
2025-08-22 15:30 ` [PATCH 28/33] arm_mpam: Track bandwidth counter state for overflow and power management James Morse
2025-08-28 0:58 ` Fenghua Yu
2025-08-22 15:30 ` [PATCH 29/33] arm_mpam: Probe for long/lwd mbwu counters James Morse
2025-08-22 15:30 ` [PATCH 30/33] arm_mpam: Use long MBWU counters if supported James Morse
2025-08-22 15:30 ` [PATCH 31/33] arm_mpam: Add helper to reset saved mbwu state James Morse
2025-08-22 15:30 ` [PATCH 32/33] arm_mpam: Add kunit test for bitmap reset James Morse
2025-08-22 15:30 ` [PATCH 33/33] arm_mpam: Add kunit tests for props_mismatch() James Morse
2025-09-02 16:59 ` Fenghua Yu
2025-08-24 17:24 ` [PATCH 00/33] arm_mpam: Add basic mpam driver Krzysztof Kozlowski
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