From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 90879CA0ED1 for ; Mon, 18 Aug 2025 13:40:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ICmPS97hbsRSk2h20NdPd9HR7vrrUY1gI8ot1bFxVrE=; b=dGR8XEZrLbyDv/H+f51BZAAecm DJLl8G6JutF9rrn7/LhOKncNKPBLQbXR/QIv5OpgqSpmtsk6cPYwW100GDOrmXTURuQMYZkW7ho7w 3/gRqeDiEMlGIzn5en7l0+GqwEVa9mqJGjaWt6U4hHCSFiOsnJ4RCxQTTk/4ORw0dkZyEGT4WeoxD +rEle5wP+fcB96v5K8EDlrQSeEb4rDvGk2jLWD1RorgHN/hiv6/MjIa5/8ec8q8jgIRj9sfecQ1Kl PAlU/KStFTtvLTiKqWLJuD8Nptr3V/HeUrZ0wiiY6jpVy3riIxVhS91pybZBubEIzFd4sm1VczOoO OJ5+BpKQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uo05d-00000007Y1d-0trH; Mon, 18 Aug 2025 13:39:57 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1unvu6-000000071Vn-3eAr for linux-arm-kernel@lists.infradead.org; Mon, 18 Aug 2025 09:11:48 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 86D291424; Mon, 18 Aug 2025 02:11:35 -0700 (PDT) Received: from J2N7QTR9R3 (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 19F0A3F58B; Mon, 18 Aug 2025 02:11:39 -0700 (PDT) Date: Mon, 18 Aug 2025 10:11:30 +0100 From: Mark Rutland To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Mark Brown , Ryan Roberts , kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/4] arm64/sysreg: Update TCR_EL1 register Message-ID: References: <20250818045759.672408-1-anshuman.khandual@arm.com> <20250818045759.672408-2-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250818045759.672408-2-anshuman.khandual@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250818_021146_945589_07F583AC X-CRM114-Status: GOOD ( 14.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Aug 18, 2025 at 10:27:56AM +0530, Anshuman Khandual wrote: > Update TCR_EL1 register fields as per latest ARM ARM DDI 0487 7.B and while > here drop an explicit sysreg definition SYS_TCR_EL1 from sysreg.h, which is > now redundant. > > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Marc Zyngier > Cc: Mark Brown > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Anshuman Khandual > --- > arch/arm64/include/asm/sysreg.h | 2 -- > arch/arm64/tools/sysreg | 52 ++++++++++++++++++++++++++++----- > 2 files changed, 44 insertions(+), 10 deletions(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index d5b5f2ae1afa..ad5c901af229 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -281,8 +281,6 @@ > #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) > #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) > > -#define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) > - > #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) > #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1) > #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2) > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index 696ab1f32a67..4bdae8bb11dc 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -4756,17 +4756,53 @@ Field 37 TBI0 > Field 36 AS > Res0 35 > Field 34:32 IPS > -Field 31:30 TG1 > -Field 29:28 SH1 > -Field 27:26 ORGN1 > -Field 25:24 IRGN1 > +UnsignedEnum 31:30 TG1 > + 0b01 16K > + 0b10 4K > + 0b11 64K > +EndEnum This is clearly not an ordered set. This should just use Enum, not UnsignedEnum. Likewise for all the other cases below. Mark. > +UnsignedEnum 29:28 SH1 > + 0b00 NONE > + 0b10 OUTER > + 0b11 INNER > +EndEnum > +UnsignedEnum 27:26 ORGN1 > + 0b00 NC > + 0b01 WBWA > + 0b10 WT > + 0b11 WBnWA > +EndEnum > +UnsignedEnum 25:24 IRGN1 > + 0b00 NC > + 0b01 WBWA > + 0b10 WT > + 0b11 WBnWA > +EndEnum > Field 23 EPD1 > Field 22 A1 > Field 21:16 T1SZ > -Field 15:14 TG0 > -Field 13:12 SH0 > -Field 11:10 ORGN0 > -Field 9:8 IRGN0 > +UnsignedEnum 15:14 TG0 > + 0b00 4K > + 0b01 64K > + 0b10 16K > +EndEnum > +UnsignedEnum 13:12 SH0 > + 0b00 NONE > + 0b10 OUTER > + 0b11 INNER > +EndEnum > +UnsignedEnum 11:10 ORGN0 > + 0b00 NC > + 0b01 WBWA > + 0b10 WT > + 0b11 WBnWA > +EndEnum > +UnsignedEnum 9:8 IRGN0 > + 0b00 NC > + 0b01 WBWA > + 0b10 WT > + 0b11 WBnWA > +EndEnum > Field 7 EPD0 > Res0 6 > Field 5:0 T0SZ > -- > 2.25.1 > >