* [PATCH v6 0/3] Add support for Variscite VAR-SOM-AM62P5 and Symphony board
@ 2025-09-04 13:22 Stefano Radaelli
2025-09-04 13:22 ` [PATCH v6 1/3] dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62P Stefano Radaelli
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Stefano Radaelli @ 2025-09-04 13:22 UTC (permalink / raw)
To: devicetree, linux-kernel
Cc: Stefano Radaelli, Nishanth Menon, Vignesh Raghavendra,
Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-kernel
This patch series adds support for the Variscite VAR-SOM-AM62P system on module
and the Symphony carrier board.
The VAR-SOM-AM62P is a compact SOM based on the TI AM62P Sitara processor,
featuring up to 8GB DDR4 memory, eMMC storage, Gigabit Ethernet, and various
peripheral interfaces. The Symphony board is a feature-rich carrier board that
showcases the SOM capabilities.
The series includes:
- Device tree bindings documentation
- SOM device tree with common peripherals
- Symphony carrier board device tree with board-specific features
The implementation follows the standard SOM + carrier board pattern where the
SOM dtsi contains only peripherals mounted on the module, while carrier-specific
interfaces are enabled in the board dts.
Tested on VAR-SOM-AM62P with Symphony carrier board.
Stefano Radaelli (3):
dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62P
arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P
arm64: dts: ti: var-som-am62p: Add support for Variscite Symphony
Board
.../devicetree/bindings/arm/ti/k3.yaml | 6 +
arch/arm64/boot/dts/ti/Makefile | 1 +
.../dts/ti/k3-am62p5-var-som-symphony.dts | 500 ++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 385 ++++++++++++++
4 files changed, 892 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
base-commit: 07d9df80082b8d1f37e05658371b087cb6738770
--
2.43.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v6 1/3] dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62P
2025-09-04 13:22 [PATCH v6 0/3] Add support for Variscite VAR-SOM-AM62P5 and Symphony board Stefano Radaelli
@ 2025-09-04 13:22 ` Stefano Radaelli
2025-09-04 13:22 ` [PATCH v6 2/3] arm64: dts: ti: Add support " Stefano Radaelli
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Stefano Radaelli @ 2025-09-04 13:22 UTC (permalink / raw)
To: devicetree, linux-kernel
Cc: Stefano Radaelli, Rob Herring, Nishanth Menon,
Vignesh Raghavendra, Tero Kristo, Krzysztof Kozlowski,
Conor Dooley, linux-arm-kernel
Add devicetree bindings for Variscite VAR-SOM-AM62P System on Module
and its carrier boards.
Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
---
v4:
- Added Acked-by
v3:
- Change compatible string to match existing mainline format
v2:
- Add symphony carrier board compatible
Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
index e80c653fa438..1cdb6464e920 100644
--- a/Documentation/devicetree/bindings/arm/ti/k3.yaml
+++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
@@ -106,6 +106,12 @@ properties:
- const: toradex,verdin-am62p # Verdin AM62P Module
- const: ti,am62p5
+ - description: K3 AM62P5 SoC Variscite SOM and Carrier Boards
+ items:
+ - const: variscite,var-som-am62p-symphony
+ - const: variscite,var-som-am62p
+ - const: ti,am62p5
+
- description: K3 AM642 SoC
items:
- enum:
--
2.43.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v6 2/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P
2025-09-04 13:22 [PATCH v6 0/3] Add support for Variscite VAR-SOM-AM62P5 and Symphony board Stefano Radaelli
2025-09-04 13:22 ` [PATCH v6 1/3] dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62P Stefano Radaelli
@ 2025-09-04 13:22 ` Stefano Radaelli
2025-09-08 18:06 ` Judith Mendez
2025-09-08 18:09 ` Judith Mendez
2025-09-04 13:22 ` [PATCH v6 3/3] arm64: dts: ti: var-som-am62p: Add support for Variscite Symphony Board Stefano Radaelli
2025-09-09 18:37 ` [PATCH v6 0/3] Add support for Variscite VAR-SOM-AM62P5 and Symphony board Judith Mendez
3 siblings, 2 replies; 9+ messages in thread
From: Stefano Radaelli @ 2025-09-04 13:22 UTC (permalink / raw)
To: devicetree, linux-kernel
Cc: Stefano Radaelli, Nishanth Menon, Vignesh Raghavendra,
Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-kernel
Add device tree support for the Variscite VAR-SOM-AM62P system on module.
This SOM is designed to be used with various carrier boards.
The module includes:
- AM62P Sitara MPU processor
- Up to 8GB of DDR4-3733 memory
- eMMC storage memory
- PS6522430 chip as a Power Management Integrated circuit (PMIC)
- Integrated 10/100/1000 Mbps Ethernet Transceiver Analog Devices ADIN1300
- Resistive touch panel interface controller TI TSC2046
- I2C interfaces
Only SOM-specific peripherals are enabled by default. Carrier board
specific interfaces are left disabled to be enabled in the respective
carrier board device trees.
Link: https://www.variscite.it/product/system-on-module-som/cortex-a53-krait/var-som-am62p-ti-sitara-am62px/
Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
---
v6:
- Removed unnecessary sdhci properties
v5:
- Update to match up with coding guidelines for device tree
v4:
- Moved every MCUs-related node into the SOM dtsi
- Removed unused audio node
v3:
- Change compatible string to match existing mainline format
- Lower case hex digits
- Generic node names
v2:
- Fixed warnings and cleanup
arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 385 ++++++++++++++++++
1 file changed, 385 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
new file mode 100644
index 000000000000..da037993574f
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
@@ -0,0 +1,385 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common dtsi for Variscite VAR-SOM-AM62P
+ *
+ * Link: https://www.variscite.com/product/system-on-module-som/cortex-a53-krait/var-som-am62p-ti-sitara-am62px/
+ *
+ * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pwm/pwm.h>
+#include "k3-am62p5.dtsi"
+
+/ {
+ compatible = "variscite,var-som-am62p", "ti,am62p5";
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ post-power-on-delay-ms = <100>;
+ power-off-delay-us = <10000>;
+ reset-gpios = <&main_gpio0 54 GPIO_ACTIVE_LOW>, /* WIFI_PWR_EN */
+ <&main_gpio0 59 GPIO_ACTIVE_LOW>; /* WIFI_EN */
+ };
+
+ mmc_pwrseq: mmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc_pwrseq>;
+ reset-gpios = <&main_gpio0 49 GPIO_ACTIVE_LOW>;
+ };
+
+ memory@80000000 {
+ /* 8G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000001 0x80000000>;
+ device_type = "memory";
+ bootph-pre-ram;
+ };
+
+ opp-table {
+ /* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-supported-hw = <0x01 0x0004>;
+ clock-latency-ns = <6000000>;
+ };
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ rtos_ipc_memory_region: rtos-ipc-memory@9b500000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9b500000 0x00 0x00300000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9b800000 0x00 0x00100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9b900000 0x00 0x00f00000>;
+ no-map;
+ };
+
+ wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9c800000 0x00 0x00100000>;
+ no-map;
+ };
+
+ wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0x9c900000 0x00 0x01e00000>;
+ no-map;
+ };
+
+ secure_tfa_ddr: tfa@9e780000 {
+ reg = <0x00 0x9e780000 0x00 0x80000>;
+ no-map;
+ };
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+ no-map;
+ };
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "On-module +V3.3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_1v8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "On-module +V1.8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <®_3v3>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_3v3_phy: regulator-3v3-phy {
+ compatible = "regulator-fixed";
+ regulator-name = "On-module +V3.3_PHY";
+ gpios = <&main_gpio0 45 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+};
+
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii1>;
+};
+
+&cpsw3g_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mdio1>;
+ status = "okay";
+
+ cpsw3g_phy0: ethernet-phy@4 {
+ compatible = "ethernet-phy-id0283.bc30";
+ reg = <4>;
+ reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <100000>;
+ };
+};
+
+&cpsw_port1 {
+ /*
+ * The required RGMII TX and RX 2ns delays are implemented directly
+ * in hardware via passive delay elements on the SOM PCB.
+ * No delay configuration is needed in software via PHY driver.
+ */
+ phy-mode = "rgmii";
+ phy-handle = <&cpsw3g_phy0>;
+ status = "okay";
+};
+
+&main_i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&main_i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&main_pmx0 {
+ pinctrl_mmc_pwrseq: main-emmc-pwrseq-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (AB23) VOUT0_DATA4.GPIO0_49 */
+ >;
+ };
+
+ pinctrl_i2c2: main-i2c2-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (T22) GPMC0_CSn2.I2C2_SCL */
+ AM62PX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (U25) GPMC0_CSn3.I2C2_SDA */
+ >;
+ };
+
+ pinctrl_i2c3: main-i2c3-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A23) UART0_CTSn.I2C3_SCL */
+ AM62PX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (C22) UART0_RTSn.I2C3_SDA */
+ >;
+ };
+
+ pinctrl_mdio1: main-mdio1-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */
+ AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */
+ >;
+ };
+
+ pinctrl_mmc2: main-mmc2-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x0120, PIN_INPUT_PULLUP, 0) /* (K24) MMC2_CMD */
+ AM62PX_IOPAD(0x0118, PIN_INPUT_PULLDOWN, 0) /* (K21) MMC2_CLK */
+ AM62PX_IOPAD(0x011c, PIN_INPUT_PULLUP, 0) /* () MMC2_CLKLB */
+ AM62PX_IOPAD(0x0114, PIN_INPUT_PULLUP, 0) /* (K23) MMC2_DAT0 */
+ AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */
+ AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */
+ AM62PX_IOPAD(0x0108, PIN_INPUT_PULLUP, 0) /* (L21) MMC2_DAT3 */
+ >;
+ };
+
+ pinctrl_rgmii1: main-rgmii1-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */
+ AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */
+ AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */
+ AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */
+ AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */
+ AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */
+ AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */
+ AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */
+ AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */
+ AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */
+ AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */
+ AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */
+ >;
+ bootph-all;
+ };
+
+ pinctrl_spi0: main-spi0-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (B21) SPI0_CLK */
+ AM62PX_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (D20) SPI0_CS0 */
+ AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B20) SPI0_D0 */
+ AM62PX_IOPAD(0x01c4, PIN_INPUT, 0) /* (C21) SPI0_D1 */
+ >;
+ };
+
+ pinctrl_uart5: main-uart5-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x00ec, PIN_INPUT, 4) /* (AC21) VOUT0_DATA13.UART5_CTSn */
+ AM62PX_IOPAD(0x00e8, PIN_OUTPUT, 4) /* (AD21) VOUT0_DATA12.UART5_RTSn */
+ AM62PX_IOPAD(0x00d0, PIN_INPUT, 4) /* (AC23) VOUT0_DATA6.UART5_RXD */
+ AM62PX_IOPAD(0x00d4, PIN_OUTPUT, 4) /* (AE23) VOUT0_DATA7.UART5_TXD */
+ >;
+ };
+
+ pinctrl_bt: main-btgrp-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x00f4, PIN_OUTPUT, 7) /* (Y20) VOUT0_DATA15.GPIO0_60 (BT_EN) */
+ >;
+ };
+
+ pinctrl_restouch: main-restouch-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x00c4, PIN_INPUT_PULLUP, 7) /* (Y23) VOUT0_DATA3.GPIO0_48 */
+ >;
+ };
+
+ pinctrl_wifi: main-wifi-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 7) /* (AC22) VOUT0_DATA9.GPIO0_54 - WIFI_PWR_EN - */
+ AM62PX_IOPAD(0x00f0, PIN_OUTPUT, 7) /* (AA20) VOUT0_DATA14.GPIO0_59 - WIFI_EN - */
+ >;
+ };
+};
+
+&mcu_pmx0 {
+ pinctrl_wkup_clkout0: wkup-clkout0-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */
+ >;
+ };
+};
+
+&main_spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0>;
+ ti,pindir-d0-out-d1-in;
+ status = "okay";
+};
+
+&main_uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "nxp,88w8987-bt";
+ };
+};
+
+&sdhci0 {
+ ti,driver-strength-ohm = <50>;
+ mmc-pwrseq = <&mmc_pwrseq>;
+ bootph-all;
+ status = "okay";
+};
+
+&sdhci2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc2>, <&pinctrl_wifi>;
+ bus-width = <4>;
+ non-removable;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ ti,fails-without-test-cd;
+ status = "okay";
+};
+
+&usbss0 {
+ ti,vbus-divider;
+};
+
+&usbss1 {
+ ti,vbus-divider;
+};
+
+&mailbox0_cluster0 {
+ status = "okay";
+
+ mbox_r5_0: mbox-r5-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+};
+
+&mailbox0_cluster1 {
+ status = "okay";
+
+ mbox_mcu_r5_0: mbox-mcu-r5-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+};
+
+&mcu_r5fss0 {
+ status = "okay";
+};
+
+&mcu_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
+ memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+ <&mcu_r5fss0_core0_memory_region>;
+};
+
+&wkup_r5fss0 {
+ status = "okay";
+};
+
+&wkup_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
+ memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
+ <&wkup_r5fss0_core0_memory_region>;
+};
+
+/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
+&mcu_gpio0 {
+ status = "reserved";
+};
+
+&mcu_gpio_intr {
+ status = "reserved";
+};
+
+&wkup_rtc0 {
+ status = "disabled";
+};
+
+&wkup_rti0 {
+ /* WKUP RTI0 is used by DM firmware */
+ status = "reserved";
+};
+
+&wkup_uart0 {
+ /* WKUP UART0 is used by DM firmware */
+ status = "reserved";
+};
+
+&main_uart1 {
+ /* Main UART1 is used by TIFS firmware */
+ status = "reserved";
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v6 3/3] arm64: dts: ti: var-som-am62p: Add support for Variscite Symphony Board
2025-09-04 13:22 [PATCH v6 0/3] Add support for Variscite VAR-SOM-AM62P5 and Symphony board Stefano Radaelli
2025-09-04 13:22 ` [PATCH v6 1/3] dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62P Stefano Radaelli
2025-09-04 13:22 ` [PATCH v6 2/3] arm64: dts: ti: Add support " Stefano Radaelli
@ 2025-09-04 13:22 ` Stefano Radaelli
2025-09-09 18:37 ` [PATCH v6 0/3] Add support for Variscite VAR-SOM-AM62P5 and Symphony board Judith Mendez
3 siblings, 0 replies; 9+ messages in thread
From: Stefano Radaelli @ 2025-09-04 13:22 UTC (permalink / raw)
To: devicetree, linux-kernel
Cc: Stefano Radaelli, Nishanth Menon, Vignesh Raghavendra,
Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-kernel
Add device tree support for the Variscite Symphony carrier board with
the VAR-SOM-AM62P system on module.
The Symphony board includes
- uSD Card support
- USB ports and OTG
- Additional Gigabit Ethernet interface
- Uart interfaces
- OV5640 Camera support
- GPIO Expander
- CAN, I2C and general purpose interfaces
Link: https://www.variscite.it/product/single-board-computers/symphony-board/
Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
---
v6:
- Fixed wrong pinmux for uSD, external pullup already mounted on DATA lines
v5:
- Update to match up with coding guidelines for device tree
v4:
- Moved every MCUs-related node into the SOM dtsi
v3:
- Change compatible string to match existing mainline format
- Fixed underscore typo
v2:
- Fixed warnings and cleanup
arch/arm64/boot/dts/ti/Makefile | 1 +
.../dts/ti/k3-am62p5-var-som-symphony.dts | 500 ++++++++++++++++++
2 files changed, 501 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index aad9177930e6..b11cbf33422d 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -38,6 +38,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62d2-evm.dtb
# Boards with AM62Px SoC
dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-am62p5-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dahlia.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dev.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-ivy.dtb
diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
new file mode 100644
index 000000000000..4bb92fde6ab8
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
@@ -0,0 +1,500 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Variscite Symphony carrier board for VAR-SOM-AM62P
+ *
+ * Link: https://www.variscite.it/product/single-board-computers/symphony-board/
+ *
+ * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
+ *
+ */
+
+/dts-v1/;
+
+#include "k3-am62p5-var-som.dtsi"
+
+/ {
+ model = "Variscite VAR-SOM-AM62P on Symphony-Board";
+ compatible = "variscite,var-som-am62p-symphony", "variscite,var-som-am62p", "ti,am62p5";
+
+ aliases {
+ ethernet0 = &cpsw_port1;
+ ethernet1 = &cpsw_port2;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ mmc2 = &sdhci2;
+ serial0 = &main_uart0;
+ serial2 = &main_uart2;
+ serial5 = &main_uart5;
+ serial6 = &main_uart6;
+ spi5 = &main_spi2;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ clk_ov5640_fixed: clock-24000000 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ button-back {
+ label = "Back";
+ linux,code = <KEY_BACK>;
+ gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
+ };
+
+ button-home {
+ label = "Home";
+ linux,code = <KEY_HOME>;
+ gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
+ };
+
+ button-menu {
+ label = "Menu";
+ linux,code = <KEY_MENU>;
+ gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led-heartbeat {
+ label = "Heartbeat";
+ linux,default-trigger = "heartbeat";
+ gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ reg_2p8v: regulator-2p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "2P8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ vin-supply = <®_3v3>;
+ regulator-always-on;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <®_3v3>;
+ regulator-always-on;
+ };
+
+ reg_1p5v: regulator-1p5v {
+ compatible = "regulator-fixed";
+ regulator-name = "1P5V";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ vin-supply = <®_3v3>;
+ regulator-always-on;
+ };
+
+ reg_sdhc1_vmmc: regulator-sdhc1 {
+ compatible = "regulator-fixed";
+ regulator-name = "+V3.3_SD";
+ vin-supply = <®_sdhc1_vmmc_int>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&main_gpio0 30 GPIO_ACTIVE_HIGH>;
+ bootph-all;
+ };
+
+ reg_sdhc1_vmmc_int: regulator-sdhc1-int {
+ compatible = "regulator-fixed";
+ regulator-name = "+V3.3_SD_INT";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sd1_vmmc>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ gpio = <&main_gpio0 53 GPIO_ACTIVE_HIGH>;
+ bootph-all;
+ };
+
+ reg_sdhc1_vqmmc: regulator-sdhci1-vqmmc {
+ compatible = "regulator-gpio";
+ regulator-name = "+V3.3_SD_VQMMC";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sd1_vqmmc>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ gpios = <&main_gpio0 56 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
+ bootph-all;
+ };
+
+ reg_ov5640_buf_en: regulator-camera-buf-en {
+ compatible = "regulator-fixed";
+ regulator-name = "ov5640_buf_en";
+ gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ transceiver1: can-phy {
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ };
+
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_extcon>;
+ label = "USB-C";
+ id-gpios = <&main_gpio1 12 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ port {
+ usb_con_hs: endpoint {
+ remote-endpoint = <&typec_hs>;
+ };
+ };
+ };
+};
+
+&cdns_csi2rx0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi0_port0: port@0 {
+ reg = <0>;
+ status = "okay";
+
+ csi2rx0_in_sensor: endpoint {
+ remote-endpoint = <&csi2_cam0>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii1>,
+ <&pinctrl_rgmii2>;
+ status = "okay";
+};
+
+&cpsw3g_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mdio1>;
+ status = "okay";
+
+ cpsw3g_phy1: ethernet-phy@5 {
+ compatible = "ethernet-phy-id0283.bc30";
+ reg = <5>;
+ reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <100000>;
+ };
+};
+
+&cpsw_port2 {
+ /*
+ * The required RGMII TX and RX 2ns delays are implemented directly
+ * in hardware via passive delay elements on the Symphony PCB.
+ * No delay configuration is needed in software via PHY driver.
+ */
+ phy-mode = "rgmii";
+ phy-handle = <&cpsw3g_phy1>;
+ status = "okay";
+};
+
+&dphy0 {
+ status = "okay";
+};
+
+&main_i2c0{
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ ov5640: camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ clocks = <&clk_ov5640_fixed>;
+ clock-names = "xclk";
+ AVDD-supply = <®_2p8v>;
+ DOVDD-supply = <®_1p8v>;
+ DVDD-supply = <®_1p5v>;
+ powerdown-gpios = <&main_gpio0 10 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5640>;
+
+ port {
+ csi2_cam0: endpoint {
+ remote-endpoint = <&csi2rx0_in_sensor>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
+ /* GPIO expander */
+ pca9534: gpio@20 {
+ compatible = "nxp,pca9534";
+ reg = <0x20>;
+ gpio-controller;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pca9534>;
+ interrupt-parent = <&main_gpio1>;
+ interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
+ #gpio-cells = <2>;
+ status = "okay";
+
+ usb3-sel-hog {
+ gpio-hog;
+ gpios = <4 0>;
+ output-low;
+ line-name = "usb3_sel";
+ };
+
+ eth-som-vselect-hog {
+ gpio-hog;
+ gpios = <6 0>;
+ output-low;
+ line-name = "eth-vselect";
+ };
+
+ eth-mdio-enable-hog {
+ gpio-hog;
+ gpios = <7 0>;
+ output-high;
+ line-name = "eth-mdio-enable";
+ };
+ };
+};
+
+&main_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ rtc@68 {
+ compatible = "dallas,ds1337";
+ reg = <0x68>;
+ };
+};
+
+&main_mcan0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mcan0>;
+ phys = <&transceiver1>;
+ status = "okay";
+};
+
+&main_pmx0 {
+ pinctrl_extcon: main-extcon-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x01a8, PIN_INPUT, 7) /* (F25) MCASP0_AFSX.GPIO1_12 */
+ >;
+ };
+
+ pinctrl_i2c0: main-i2c0-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B25) I2C0_SCL */
+ AM62PX_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A24) I2C0_SDA */
+ >;
+ };
+
+ pinctrl_i2c1: main-i2c1-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C24) I2C1_SCL */
+ AM62PX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B24) I2C1_SDA */
+ >;
+ bootph-all;
+ };
+
+ pinctrl_mcan0: main-mcan0-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x01dc, PIN_INPUT, 0) /* (F20) MCAN0_RX */
+ AM62PX_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (B23) MCAN0_TX */
+ >;
+ };
+
+ pinctrl_mmc1: main-mmc1-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x023c, PIN_INPUT, 0) /* (H20) MMC1_CMD */
+ AM62PX_IOPAD(0x0234, PIN_OUTPUT, 0) /* (J24) MMC1_CLK */
+ AM62PX_IOPAD(0x0230, PIN_INPUT, 0) /* (H21) MMC1_DAT0 */
+ AM62PX_IOPAD(0x022c, PIN_INPUT, 0) /* (H23) MMC1_DAT1 */
+ AM62PX_IOPAD(0x0228, PIN_INPUT, 0) /* (H22) MMC1_DAT2 */
+ AM62PX_IOPAD(0x0224, PIN_INPUT, 0) /* (H25) MMC1_DAT3 */
+ AM62PX_IOPAD(0x0240, PIN_INPUT, 0) /* (D23) MMC1_SDCD */
+ >;
+ bootph-all;
+ };
+
+ pinctrl_rgmii2: main-rgmii2-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x0184, PIN_INPUT, 0) /* (E19) RGMII2_RD0 */
+ AM62PX_IOPAD(0x0188, PIN_INPUT, 0) /* (E16) RGMII2_RD1 */
+ AM62PX_IOPAD(0x018c, PIN_INPUT, 0) /* (E17) RGMII2_RD2 */
+ AM62PX_IOPAD(0x0190, PIN_INPUT, 0) /* (C19) RGMII2_RD3 */
+ AM62PX_IOPAD(0x0180, PIN_INPUT, 0) /* (D19) RGMII2_RXC */
+ AM62PX_IOPAD(0x017c, PIN_INPUT, 0) /* (F19) RGMII2_RX_CTL */
+ AM62PX_IOPAD(0x016c, PIN_INPUT, 0) /* (B19) RGMII2_TD0 */
+ AM62PX_IOPAD(0x0170, PIN_INPUT, 0) /* (A21) RGMII2_TD1 */
+ AM62PX_IOPAD(0x0174, PIN_INPUT, 0) /* (D17) RGMII2_TD2 */
+ AM62PX_IOPAD(0x0178, PIN_INPUT, 0) /* (A19) RGMII2_TD3 */
+ AM62PX_IOPAD(0x0168, PIN_INPUT_PULLDOWN, 0) /* (D16) RGMII2_TXC */
+ AM62PX_IOPAD(0x0164, PIN_INPUT, 0) /* (A20) RGMII2_TX_CTL */
+ >;
+ };
+
+ pinctrl_spi2: main-spi2-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x01b0, PIN_INPUT, 1) /* (G20) MCASP0_ACLKR.SPI2_CLK */
+ AM62PX_IOPAD(0x0194, PIN_OUTPUT, 1) /* (D25) MCASP0_AXR3.SPI2_D0 */
+ AM62PX_IOPAD(0x0198, PIN_INPUT, 1) /* (E25) MCASP0_AXR2.SPI2_D1 */
+ AM62PX_IOPAD(0x01ac, PIN_OUTPUT, 7) /* (G23) MCASP0_AFSR.GPIO1_13 */
+ >;
+ };
+
+ pinctrl_uart0: main-uart0-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */
+ AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */
+ >;
+ bootph-all;
+ };
+
+ pinctrl_uart2: main-uart2-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x005c, PIN_INPUT_PULLUP, 2) /* (AC25) GPMC0_AD8.UART2_RXD */
+ AM62PX_IOPAD(0x0060, PIN_OUTPUT, 2) /* (AB25) GPMC0_AD9.UART2_TXD */
+ >;
+ };
+
+ pinctrl_uart6: main-uart6-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x009c, PIN_INPUT_PULLUP, 3) /* (AD24) GPMC0_WAIT1.UART6_RXD */
+ AM62PX_IOPAD(0x0244, PIN_OUTPUT, 1) /* (D24) MMC1_SDWP.UART6_TXD */
+ >;
+ };
+
+ pinctrl_usb1: main-usb1-default-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (G21) USB1_DRVVBUS */
+ >;
+ };
+
+ pinctrl_ov5640: main-ov5640-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x0028, PIN_OUTPUT, 7) /* (N20) OSPI0_D7.GPIO0_10 */
+ AM62PX_IOPAD(0x0054, PIN_OUTPUT, 7) /* (V24) GPMC0_AD6.GPIO0_21 */
+ AM62PX_IOPAD(0x0058, PIN_OUTPUT, 7) /* (W25) GPMC0_AD7.GPIO0_22 */
+ >;
+ };
+
+ pinctrl_pca9534: main-pca9534-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x01f0, PIN_INPUT, 7) /* (C25) EXT_REFCLK1.GPIO1_30 */
+ >;
+ };
+
+ pinctrl_sd1_vmmc: main-sd1-vmmc-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AC24) GPMC0_AD15.GPIO0_30 */
+ AM62PX_IOPAD(0x00d8, PIN_OUTPUT, 7) /* (AE22) VOUT0_DATA8.GPIO0_53 */
+ >;
+ bootph-all;
+ };
+
+ pinctrl_sd1_vqmmc: main-sd1-vqmmc-pins {
+ pinctrl-single,pins = <
+ AM62PX_IOPAD(0x00e4, PIN_OUTPUT, 7) /* (AE21) VOUT0_DATA11.GPIO0_56 */
+ >;
+ bootph-all;
+ };
+};
+
+&main_spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2>;
+ ti,pindir-d0-out-d1-in;
+ cs-gpios = <&main_gpio1 13 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ status = "okay";
+};
+
+&main_uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&main_uart6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart6>;
+ status = "okay";
+};
+
+&sdhci1 {
+ /* SD Card */
+ vmmc-supply = <®_sdhc1_vmmc>;
+ vqmmc-supply = <®_sdhc1_vqmmc>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mmc1>;
+ disable-wp;
+ bootph-all;
+ status="okay";
+};
+
+&ti_csi2rx0 {
+ status = "okay";
+};
+
+&usb0 {
+ usb-role-switch;
+ status = "okay";
+
+ port {
+ typec_hs: endpoint {
+ remote-endpoint = <&usb_con_hs>;
+ };
+ };
+};
+
+&usb1 {
+ dr_mode = "host";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ status = "okay";
+};
+
+&usbss0 {
+ status = "okay";
+};
+
+&usbss1 {
+ status = "okay";
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v6 2/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P
2025-09-04 13:22 ` [PATCH v6 2/3] arm64: dts: ti: Add support " Stefano Radaelli
@ 2025-09-08 18:06 ` Judith Mendez
2025-09-09 6:45 ` Stefano Radaelli
2025-09-08 18:09 ` Judith Mendez
1 sibling, 1 reply; 9+ messages in thread
From: Judith Mendez @ 2025-09-08 18:06 UTC (permalink / raw)
To: Stefano Radaelli, devicetree, linux-kernel
Cc: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel
Hi Stefano,
On 9/4/25 8:22 AM, Stefano Radaelli wrote:
> Add device tree support for the Variscite VAR-SOM-AM62P system on module.
> This SOM is designed to be used with various carrier boards.
>
> The module includes:
> - AM62P Sitara MPU processor
> - Up to 8GB of DDR4-3733 memory
> - eMMC storage memory
> - PS6522430 chip as a Power Management Integrated circuit (PMIC)
> - Integrated 10/100/1000 Mbps Ethernet Transceiver Analog Devices ADIN1300
> - Resistive touch panel interface controller TI TSC2046
> - I2C interfaces
>
> Only SOM-specific peripherals are enabled by default. Carrier board
> specific interfaces are left disabled to be enabled in the respective
> carrier board device trees.
>
> Link: https://www.variscite.it/product/system-on-module-som/cortex-a53-krait/var-som-am62p-ti-sitara-am62px/
>
> Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
> ---
> v6:
> - Removed unnecessary sdhci properties
> v5:
> - Update to match up with coding guidelines for device tree
> v4:
> - Moved every MCUs-related node into the SOM dtsi
> - Removed unused audio node
> v3:
> - Change compatible string to match existing mainline format
> - Lower case hex digits
> - Generic node names
> v2:
> - Fixed warnings and cleanup
>
> arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 385 ++++++++++++++++++
> 1 file changed, 385 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> new file mode 100644
> index 000000000000..da037993574f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> @@ -0,0 +1,385 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Common dtsi for Variscite VAR-SOM-AM62P
> + *
> + * Link: https://www.variscite.com/product/system-on-module-som/cortex-a53-krait/var-som-am62p-ti-sitara-am62px/
> + *
> + * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/pwm/pwm.h>
> +#include "k3-am62p5.dtsi"
> +
> +/ {
> + compatible = "variscite,var-som-am62p", "ti,am62p5";
> +
> + wifi_pwrseq: wifi-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + post-power-on-delay-ms = <100>;
> + power-off-delay-us = <10000>;
> + reset-gpios = <&main_gpio0 54 GPIO_ACTIVE_LOW>, /* WIFI_PWR_EN */
> + <&main_gpio0 59 GPIO_ACTIVE_LOW>; /* WIFI_EN */
> + };
> +
> + mmc_pwrseq: mmc-pwrseq {
> + compatible = "mmc-pwrseq-emmc";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_mmc_pwrseq>;
> + reset-gpios = <&main_gpio0 49 GPIO_ACTIVE_LOW>;
> + };
> +
> + memory@80000000 {
> + /* 8G RAM */
> + reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
> + <0x00000008 0x80000000 0x00000001 0x80000000>;
> + device_type = "memory";
> + bootph-pre-ram;
> + };
> +
> + opp-table {
> + /* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */
> + opp-1400000000 {
> + opp-hz = /bits/ 64 <1400000000>;
> + opp-supported-hw = <0x01 0x0004>;
> + clock-latency-ns = <6000000>;
> + };
> + };
> +
> + reserved_memory: reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + rtos_ipc_memory_region: rtos-ipc-memory@9b500000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9b500000 0x00 0x00300000>;
> + no-map;
> + };
> +
> + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9b800000 0x00 0x00100000>;
> + no-map;
> + };
> +
> + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9b900000 0x00 0x00f00000>;
> + no-map;
> + };
Perhaps it will be a good idea to do the same refactoring as this:
https://lore.kernel.org/linux-arm-kernel/20250905051846.1189612-30-b-padhi@ti.com/
Meaning we drop the memory carve-outs for MCU R5SS here.
> +
> + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9c800000 0x00 0x00100000>;
> + no-map;
> + };
> +
> + wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9c900000 0x00 0x01e00000>;
> + no-map;
> + };
> +
> + secure_tfa_ddr: tfa@9e780000 {
> + reg = <0x00 0x9e780000 0x00 0x80000>;
> + no-map;
> + };
> +
> + secure_ddr: optee@9e800000 {
> + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
> + no-map;
> + };
> + };
> +
> + reg_3v3: regulator-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "On-module +V3.3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + reg_1v8: regulator-1v8 {
> + compatible = "regulator-fixed";
> + regulator-name = "On-module +V1.8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + vin-supply = <®_3v3>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + reg_3v3_phy: regulator-3v3-phy {
> + compatible = "regulator-fixed";
> + regulator-name = "On-module +V3.3_PHY";
> + gpios = <&main_gpio0 45 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + regulator-always-on;
> + };
> +};
> +
> +&cpsw3g {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rgmii1>;
> +};
> +
> +&cpsw3g_mdio {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_mdio1>;
> + status = "okay";
> +
> + cpsw3g_phy0: ethernet-phy@4 {
> + compatible = "ethernet-phy-id0283.bc30";
> + reg = <4>;
> + reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <10000>;
> + reset-deassert-us = <100000>;
> + };
> +};
> +
> +&cpsw_port1 {
> + /*
> + * The required RGMII TX and RX 2ns delays are implemented directly
> + * in hardware via passive delay elements on the SOM PCB.
> + * No delay configuration is needed in software via PHY driver.
> + */
> + phy-mode = "rgmii";
> + phy-handle = <&cpsw3g_phy0>;
> + status = "okay";
> +};
> +
> +&main_i2c2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + clock-frequency = <400000>;
> + status = "okay";
> +};
> +
> +&main_i2c3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + clock-frequency = <400000>;
> + status = "okay";
> +};
> +
> +&main_pmx0 {
> + pinctrl_mmc_pwrseq: main-emmc-pwrseq-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (AB23) VOUT0_DATA4.GPIO0_49 */
> + >;
> + };
> +
> + pinctrl_i2c2: main-i2c2-default-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (T22) GPMC0_CSn2.I2C2_SCL */
> + AM62PX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (U25) GPMC0_CSn3.I2C2_SDA */
> + >;
> + };
> +
> + pinctrl_i2c3: main-i2c3-default-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A23) UART0_CTSn.I2C3_SCL */
> + AM62PX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (C22) UART0_RTSn.I2C3_SDA */
> + >;
> + };
> +
> + pinctrl_mdio1: main-mdio1-default-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */
> + AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */
> + >;
> + };
> +
> + pinctrl_mmc2: main-mmc2-default-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x0120, PIN_INPUT_PULLUP, 0) /* (K24) MMC2_CMD */
> + AM62PX_IOPAD(0x0118, PIN_INPUT_PULLDOWN, 0) /* (K21) MMC2_CLK */
> + AM62PX_IOPAD(0x011c, PIN_INPUT_PULLUP, 0) /* () MMC2_CLKLB */
> + AM62PX_IOPAD(0x0114, PIN_INPUT_PULLUP, 0) /* (K23) MMC2_DAT0 */
> + AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */
> + AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */
> + AM62PX_IOPAD(0x0108, PIN_INPUT_PULLUP, 0) /* (L21) MMC2_DAT3 */
> + >;
> + };
> +
> + pinctrl_rgmii1: main-rgmii1-default-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */
> + AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */
> + AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */
> + AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */
> + AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */
> + AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */
> + AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */
> + AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */
> + AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */
> + AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */
> + AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */
> + AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */
> + >;
> + bootph-all;
> + };
> +
> + pinctrl_spi0: main-spi0-default-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (B21) SPI0_CLK */
> + AM62PX_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (D20) SPI0_CS0 */
> + AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B20) SPI0_D0 */
> + AM62PX_IOPAD(0x01c4, PIN_INPUT, 0) /* (C21) SPI0_D1 */
> + >;
> + };
> +
> + pinctrl_uart5: main-uart5-default-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x00ec, PIN_INPUT, 4) /* (AC21) VOUT0_DATA13.UART5_CTSn */
> + AM62PX_IOPAD(0x00e8, PIN_OUTPUT, 4) /* (AD21) VOUT0_DATA12.UART5_RTSn */
> + AM62PX_IOPAD(0x00d0, PIN_INPUT, 4) /* (AC23) VOUT0_DATA6.UART5_RXD */
> + AM62PX_IOPAD(0x00d4, PIN_OUTPUT, 4) /* (AE23) VOUT0_DATA7.UART5_TXD */
> + >;
> + };
> +
> + pinctrl_bt: main-btgrp-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x00f4, PIN_OUTPUT, 7) /* (Y20) VOUT0_DATA15.GPIO0_60 (BT_EN) */
> + >;
> + };
> +
> + pinctrl_restouch: main-restouch-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x00c4, PIN_INPUT_PULLUP, 7) /* (Y23) VOUT0_DATA3.GPIO0_48 */
> + >;
> + };
> +
> + pinctrl_wifi: main-wifi-default-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 7) /* (AC22) VOUT0_DATA9.GPIO0_54 - WIFI_PWR_EN - */
> + AM62PX_IOPAD(0x00f0, PIN_OUTPUT, 7) /* (AA20) VOUT0_DATA14.GPIO0_59 - WIFI_EN - */
> + >;
> + };
> +};
> +
> +&mcu_pmx0 {
> + pinctrl_wkup_clkout0: wkup-clkout0-default-pins {
> + pinctrl-single,pins = <
> + AM62PX_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */
> + >;
> + };
> +};
> +
> +&main_spi0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_spi0>;
> + ti,pindir-d0-out-d1-in;
> + status = "okay";
> +};
> +
> +&main_uart5 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>;
> + uart-has-rtscts;
> + status = "okay";
> +
> + bluetooth {
> + compatible = "nxp,88w8987-bt";
> + };
> +};
> +
> +&sdhci0 {
> + ti,driver-strength-ohm = <50>;
> + mmc-pwrseq = <&mmc_pwrseq>;
> + bootph-all;
> + status = "okay";
> +};
> +
> +&sdhci2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_mmc2>, <&pinctrl_wifi>;
> + bus-width = <4>;
> + non-removable;
> + keep-power-in-suspend;
> + mmc-pwrseq = <&wifi_pwrseq>;
> + ti,fails-without-test-cd;
> + status = "okay";
> +};
> +
> +&usbss0 {
> + ti,vbus-divider;
> +};
> +
> +&usbss1 {
> + ti,vbus-divider;
> +};
> +
> +&mailbox0_cluster0 {
> + status = "okay";
> +
> + mbox_r5_0: mbox-r5-0 {
> + ti,mbox-rx = <0 0 0>;
> + ti,mbox-tx = <1 0 0>;
> + };
> +};
> +
> +&mailbox0_cluster1 {
> + status = "okay";
> +
> + mbox_mcu_r5_0: mbox-mcu-r5-0 {
> + ti,mbox-rx = <0 0 0>;
> + ti,mbox-tx = <1 0 0>;
> + };
> +};
> +
> +&mcu_r5fss0 {
> + status = "okay";
> +};
> +
> +&mcu_r5fss0_core0 {
> + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
> + memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
> + <&mcu_r5fss0_core0_memory_region>;
> +};
> +
> +&wkup_r5fss0 {
> + status = "okay";
> +};
> +
> +&wkup_r5fss0_core0 {
> + mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
> + memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
> + <&wkup_r5fss0_core0_memory_region>;
> +};
> +
> +/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
> +&mcu_gpio0 {
> + status = "reserved";
> +};
And also drop the IPC stuff above.
> +
> +&mcu_gpio_intr {
> + status = "reserved";
> +};
> +
> +&wkup_rtc0 {
> + status = "disabled";
> +};
> +
> +&wkup_rti0 {
> + /* WKUP RTI0 is used by DM firmware */
> + status = "reserved";
> +};
> +
> +&wkup_uart0 {
> + /* WKUP UART0 is used by DM firmware */
> + status = "reserved";
> +};
> +
> +&main_uart1 {
> + /* Main UART1 is used by TIFS firmware */
> + status = "reserved";
> +};
And include:
+#include "k3-am62p-ti-ipc-firmware.dtsi"
so that this SOM can be left in a refactored state like all other DT.
Of course, this means this series would have a dependency on beleswar's
series:
https://lore.kernel.org/linux-arm-kernel/20250905051846.1189612-1-b-padhi@ti.com/
Just a suggestion here. (:
~ Judith
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v6 2/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P
2025-09-04 13:22 ` [PATCH v6 2/3] arm64: dts: ti: Add support " Stefano Radaelli
2025-09-08 18:06 ` Judith Mendez
@ 2025-09-08 18:09 ` Judith Mendez
1 sibling, 0 replies; 9+ messages in thread
From: Judith Mendez @ 2025-09-08 18:09 UTC (permalink / raw)
To: Stefano Radaelli, devicetree, linux-kernel
Cc: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel
Hi,
On 9/4/25 8:22 AM, Stefano Radaelli wrote:
> Add device tree support for the Variscite VAR-SOM-AM62P system on module.
> This SOM is designed to be used with various carrier boards.
>
> The module includes:
> - AM62P Sitara MPU processor
> - Up to 8GB of DDR4-3733 memory
> - eMMC storage memory
> - PS6522430 chip as a Power Management Integrated circuit (PMIC)
> - Integrated 10/100/1000 Mbps Ethernet Transceiver Analog Devices ADIN1300
> - Resistive touch panel interface controller TI TSC2046
> - I2C interfaces
>
> Only SOM-specific peripherals are enabled by default. Carrier board
> specific interfaces are left disabled to be enabled in the respective
> carrier board device trees.
>
> Link: https://www.variscite.it/product/system-on-module-som/cortex-a53-krait/var-som-am62p-ti-sitara-am62px/
>
> Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
> ---
> v6:
> - Removed unnecessary sdhci properties
> v5:
> - Update to match up with coding guidelines for device tree
> v4:
> - Moved every MCUs-related node into the SOM dtsi
> - Removed unused audio node
> v3:
> - Change compatible string to match existing mainline format
> - Lower case hex digits
> - Generic node names
> v2:
> - Fixed warnings and cleanup
>
> arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 385 ++++++++++++++++++
> 1 file changed, 385 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> new file mode 100644
> index 000000000000..da037993574f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> @@ -0,0 +1,385 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Common dtsi for Variscite VAR-SOM-AM62P
> + *
> + * Link: https://www.variscite.com/product/system-on-module-som/cortex-a53-krait/var-som-am62p-ti-sitara-am62px/
> + *
> + * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/pwm/pwm.h>
> +#include "k3-am62p5.dtsi"
> +
> +/ {
> + compatible = "variscite,var-som-am62p", "ti,am62p5";
> +
> + wifi_pwrseq: wifi-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + post-power-on-delay-ms = <100>;
> + power-off-delay-us = <10000>;
> + reset-gpios = <&main_gpio0 54 GPIO_ACTIVE_LOW>, /* WIFI_PWR_EN */
> + <&main_gpio0 59 GPIO_ACTIVE_LOW>; /* WIFI_EN */
> + };
> +
> + mmc_pwrseq: mmc-pwrseq {
> + compatible = "mmc-pwrseq-emmc";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_mmc_pwrseq>;
> + reset-gpios = <&main_gpio0 49 GPIO_ACTIVE_LOW>;
> + };
> +
> + memory@80000000 {
> + /* 8G RAM */
> + reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
> + <0x00000008 0x80000000 0x00000001 0x80000000>;
> + device_type = "memory";
> + bootph-pre-ram;
> + };
> +
> + opp-table {
> + /* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */
> + opp-1400000000 {
> + opp-hz = /bits/ 64 <1400000000>;
> + opp-supported-hw = <0x01 0x0004>;
> + clock-latency-ns = <6000000>;
> + };
> + };
> +
> + reserved_memory: reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + rtos_ipc_memory_region: rtos-ipc-memory@9b500000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9b500000 0x00 0x00300000>;
> + no-map;
> + };
> +
> + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9b800000 0x00 0x00100000>;
> + no-map;
> + };
> +
> + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9b900000 0x00 0x00f00000>;
> + no-map;
> + };
> +
> + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9c800000 0x00 0x00100000>;
> + no-map;
> + };
> +
> + wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 {
> + compatible = "shared-dma-pool";
> + reg = <0x00 0x9c900000 0x00 0x01e00000>;
> + no-map;
> + };
> +
> + secure_tfa_ddr: tfa@9e780000 {
> + reg = <0x00 0x9e780000 0x00 0x80000>;
> + no-map;
> + };
> +
> + secure_ddr: optee@9e800000 {
> + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
> + no-map;
> + };
> + };
> +
> + reg_3v3: regulator-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "On-module +V3.3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + reg_1v8: regulator-1v8 {
> + compatible = "regulator-fixed";
> + regulator-name = "On-module +V1.8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + vin-supply = <®_3v3>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + reg_3v3_phy: regulator-3v3-phy {
> + compatible = "regulator-fixed";
> + regulator-name = "On-module +V3.3_PHY";
> + gpios = <&main_gpio0 45 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + regulator-always-on;
> + };
> +};
> +
> +&cpsw3g {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rgmii1>;
> +};
> +
> +&cpsw3g_mdio {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_mdio1>;
> + status = "okay";
> +
> + cpsw3g_phy0: ethernet-phy@4 {
> + compatible = "ethernet-phy-id0283.bc30";
> + reg = <4>;
> + reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <10000>;
> + reset-deassert-us = <100000>;
> + };
> +};
> +
> +&cpsw_port1 {
> + /*
> + * The required RGMII TX and RX 2ns delays are implemented directly
> + * in hardware via passive delay elements on the SOM PCB.
> + * No delay configuration is needed in software via PHY driver.
> + */
> + phy-mode = "rgmii";
> + phy-handle = <&cpsw3g_phy0>;
> + status = "okay";
> +};
> +
> +&main_i2c2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + clock-frequency = <400000>;
> + status = "okay";
> +};
> +
> +&main_i2c3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + clock-frequency = <400000>;
> + status = "okay";
> +};
> +
> +&main_pmx0 {
> + pinctrl_mmc_pwrseq: main-emmc-pwrseq-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (AB23) VOUT0_DATA4.GPIO0_49 */
> + >;
> + };
> +
> + pinctrl_i2c2: main-i2c2-default-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (T22) GPMC0_CSn2.I2C2_SCL */
> + AM62PX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (U25) GPMC0_CSn3.I2C2_SDA */
> + >;
> + };
> +
> + pinctrl_i2c3: main-i2c3-default-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A23) UART0_CTSn.I2C3_SCL */
> + AM62PX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (C22) UART0_RTSn.I2C3_SDA */
> + >;
> + };
> +
> + pinctrl_mdio1: main-mdio1-default-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */
> + AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */
> + >;
> + };
> +
> + pinctrl_mmc2: main-mmc2-default-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x0120, PIN_INPUT_PULLUP, 0) /* (K24) MMC2_CMD */
> + AM62PX_IOPAD(0x0118, PIN_INPUT_PULLDOWN, 0) /* (K21) MMC2_CLK */
> + AM62PX_IOPAD(0x011c, PIN_INPUT_PULLUP, 0) /* () MMC2_CLKLB */
> + AM62PX_IOPAD(0x0114, PIN_INPUT_PULLUP, 0) /* (K23) MMC2_DAT0 */
> + AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */
> + AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */
> + AM62PX_IOPAD(0x0108, PIN_INPUT_PULLUP, 0) /* (L21) MMC2_DAT3 */
> + >;
> + };
> +
> + pinctrl_rgmii1: main-rgmii1-default-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */
> + AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */
> + AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */
> + AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */
> + AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */
> + AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */
> + AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */
> + AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */
> + AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */
> + AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */
> + AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */
> + AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */
> + >;
> + bootph-all;
> + };
> +
> + pinctrl_spi0: main-spi0-default-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (B21) SPI0_CLK */
> + AM62PX_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (D20) SPI0_CS0 */
> + AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B20) SPI0_D0 */
> + AM62PX_IOPAD(0x01c4, PIN_INPUT, 0) /* (C21) SPI0_D1 */
> + >;
> + };
> +
> + pinctrl_uart5: main-uart5-default-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x00ec, PIN_INPUT, 4) /* (AC21) VOUT0_DATA13.UART5_CTSn */
> + AM62PX_IOPAD(0x00e8, PIN_OUTPUT, 4) /* (AD21) VOUT0_DATA12.UART5_RTSn */
> + AM62PX_IOPAD(0x00d0, PIN_INPUT, 4) /* (AC23) VOUT0_DATA6.UART5_RXD */
> + AM62PX_IOPAD(0x00d4, PIN_OUTPUT, 4) /* (AE23) VOUT0_DATA7.UART5_TXD */
> + >;
> + };
> +
> + pinctrl_bt: main-btgrp-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x00f4, PIN_OUTPUT, 7) /* (Y20) VOUT0_DATA15.GPIO0_60 (BT_EN) */
> + >;
> + };
> +
> + pinctrl_restouch: main-restouch-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x00c4, PIN_INPUT_PULLUP, 7) /* (Y23) VOUT0_DATA3.GPIO0_48 */
> + >;
> + };
> +
> + pinctrl_wifi: main-wifi-default-pins {
> + pinctrl-single,pins = <
> + AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 7) /* (AC22) VOUT0_DATA9.GPIO0_54 - WIFI_PWR_EN - */
> + AM62PX_IOPAD(0x00f0, PIN_OUTPUT, 7) /* (AA20) VOUT0_DATA14.GPIO0_59 - WIFI_EN - */
> + >;
> + };
> +};
> +
> +&mcu_pmx0 {
> + pinctrl_wkup_clkout0: wkup-clkout0-default-pins {
> + pinctrl-single,pins = <
> + AM62PX_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */
> + >;
> + };
> +};
> +
> +&main_spi0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_spi0>;
> + ti,pindir-d0-out-d1-in;
> + status = "okay";
> +};
> +
> +&main_uart5 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>;
> + uart-has-rtscts;
> + status = "okay";
> +
> + bluetooth {
> + compatible = "nxp,88w8987-bt";
> + };
> +};
> +
> +&sdhci0 {
Nit: Perhaps we can put comment for what device is attached to this
interface?
> + ti,driver-strength-ohm = <50>;
> + mmc-pwrseq = <&mmc_pwrseq>;
> + bootph-all;
> + status = "okay";
> +};
> +
> +&sdhci2 {
Same comment here
~ Judith
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_mmc2>, <&pinctrl_wifi>;
> + bus-width = <4>;
> + non-removable;
> + keep-power-in-suspend;
> + mmc-pwrseq = <&wifi_pwrseq>;
> + ti,fails-without-test-cd;
> + status = "okay";
> +};
> +
> +&usbss0 {
> + ti,vbus-divider;
> +};
> +
> +&usbss1 {
> + ti,vbus-divider;
> +};
> +
> +&mailbox0_cluster0 {
> + status = "okay";
> +
> + mbox_r5_0: mbox-r5-0 {
> + ti,mbox-rx = <0 0 0>;
> + ti,mbox-tx = <1 0 0>;
> + };
> +};
> +
> +&mailbox0_cluster1 {
> + status = "okay";
> +
> + mbox_mcu_r5_0: mbox-mcu-r5-0 {
> + ti,mbox-rx = <0 0 0>;
> + ti,mbox-tx = <1 0 0>;
> + };
> +};
> +
> +&mcu_r5fss0 {
> + status = "okay";
> +};
> +
> +&mcu_r5fss0_core0 {
> + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
> + memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
> + <&mcu_r5fss0_core0_memory_region>;
> +};
> +
> +&wkup_r5fss0 {
> + status = "okay";
> +};
> +
> +&wkup_r5fss0_core0 {
> + mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
> + memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
> + <&wkup_r5fss0_core0_memory_region>;
> +};
> +
> +/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
> +&mcu_gpio0 {
> + status = "reserved";
> +};
> +
> +&mcu_gpio_intr {
> + status = "reserved";
> +};
> +
> +&wkup_rtc0 {
> + status = "disabled";
> +};
> +
> +&wkup_rti0 {
> + /* WKUP RTI0 is used by DM firmware */
> + status = "reserved";
> +};
> +
> +&wkup_uart0 {
> + /* WKUP UART0 is used by DM firmware */
> + status = "reserved";
> +};
> +
> +&main_uart1 {
> + /* Main UART1 is used by TIFS firmware */
> + status = "reserved";
> +};
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v6 2/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P
2025-09-08 18:06 ` Judith Mendez
@ 2025-09-09 6:45 ` Stefano Radaelli
2025-09-09 18:35 ` Judith Mendez
0 siblings, 1 reply; 9+ messages in thread
From: Stefano Radaelli @ 2025-09-09 6:45 UTC (permalink / raw)
To: Judith Mendez
Cc: devicetree, linux-kernel, Nishanth Menon, Vignesh Raghavendra,
Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-kernel
Hi Judith,
On Mon, Sep 08, 2025 at 01:06:45PM -0500, Judith Mendez wrote:
> Hi Stefano,
>
> On 9/4/25 8:22 AM, Stefano Radaelli wrote:
> > Add device tree support for the Variscite VAR-SOM-AM62P system on module.
> > This SOM is designed to be used with various carrier boards.
> >
> > The module includes:
> > - AM62P Sitara MPU processor
> > - Up to 8GB of DDR4-3733 memory
> > - eMMC storage memory
> > - PS6522430 chip as a Power Management Integrated circuit (PMIC)
> > - Integrated 10/100/1000 Mbps Ethernet Transceiver Analog Devices ADIN1300
> > - Resistive touch panel interface controller TI TSC2046
> > - I2C interfaces
> >
> > Only SOM-specific peripherals are enabled by default. Carrier board
> > specific interfaces are left disabled to be enabled in the respective
> > carrier board device trees.
> >
> > Link: https://www.variscite.it/product/system-on-module-som/cortex-a53-krait/var-som-am62p-ti-sitara-am62px/
> >
> > Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
> > ---
> > v6:
> > - Removed unnecessary sdhci properties
> > v5:
> > - Update to match up with coding guidelines for device tree
> > v4:
> > - Moved every MCUs-related node into the SOM dtsi
> > - Removed unused audio node
> > v3:
> > - Change compatible string to match existing mainline format
> > - Lower case hex digits
> > - Generic node names
> > v2:
> > - Fixed warnings and cleanup
> >
> > arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 385 ++++++++++++++++++
> > 1 file changed, 385 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> > new file mode 100644
> > index 000000000000..da037993574f
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> > @@ -0,0 +1,385 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Common dtsi for Variscite VAR-SOM-AM62P
> > + *
> > + * Link: https://www.variscite.com/product/system-on-module-som/cortex-a53-krait/var-som-am62p-ti-sitara-am62px/
> > + *
> > + * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
> > + *
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/input/input.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/leds/common.h>
> > +#include <dt-bindings/pwm/pwm.h>
> > +#include "k3-am62p5.dtsi"
> > +
> > +/ {
> > + compatible = "variscite,var-som-am62p", "ti,am62p5";
> > +
> > + wifi_pwrseq: wifi-pwrseq {
> > + compatible = "mmc-pwrseq-simple";
> > + post-power-on-delay-ms = <100>;
> > + power-off-delay-us = <10000>;
> > + reset-gpios = <&main_gpio0 54 GPIO_ACTIVE_LOW>, /* WIFI_PWR_EN */
> > + <&main_gpio0 59 GPIO_ACTIVE_LOW>; /* WIFI_EN */
> > + };
> > +
> > + mmc_pwrseq: mmc-pwrseq {
> > + compatible = "mmc-pwrseq-emmc";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_mmc_pwrseq>;
> > + reset-gpios = <&main_gpio0 49 GPIO_ACTIVE_LOW>;
> > + };
> > +
> > + memory@80000000 {
> > + /* 8G RAM */
> > + reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
> > + <0x00000008 0x80000000 0x00000001 0x80000000>;
> > + device_type = "memory";
> > + bootph-pre-ram;
> > + };
> > +
> > + opp-table {
> > + /* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */
> > + opp-1400000000 {
> > + opp-hz = /bits/ 64 <1400000000>;
> > + opp-supported-hw = <0x01 0x0004>;
> > + clock-latency-ns = <6000000>;
> > + };
> > + };
> > +
> > + reserved_memory: reserved-memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + rtos_ipc_memory_region: rtos-ipc-memory@9b500000 {
> > + compatible = "shared-dma-pool";
> > + reg = <0x00 0x9b500000 0x00 0x00300000>;
> > + no-map;
> > + };
> > +
> > + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 {
> > + compatible = "shared-dma-pool";
> > + reg = <0x00 0x9b800000 0x00 0x00100000>;
> > + no-map;
> > + };
> > +
> > + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 {
> > + compatible = "shared-dma-pool";
> > + reg = <0x00 0x9b900000 0x00 0x00f00000>;
> > + no-map;
> > + };
>
> Perhaps it will be a good idea to do the same refactoring as this:
>
> https://lore.kernel.org/linux-arm-kernel/20250905051846.1189612-30-b-padhi@ti.com/
>
> Meaning we drop the memory carve-outs for MCU R5SS here.
>
>
> > +
> > + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
> > + compatible = "shared-dma-pool";
> > + reg = <0x00 0x9c800000 0x00 0x00100000>;
> > + no-map;
> > + };
> > +
> > + wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 {
> > + compatible = "shared-dma-pool";
> > + reg = <0x00 0x9c900000 0x00 0x01e00000>;
> > + no-map;
> > + };
> > +
> > + secure_tfa_ddr: tfa@9e780000 {
> > + reg = <0x00 0x9e780000 0x00 0x80000>;
> > + no-map;
> > + };
> > +
> > + secure_ddr: optee@9e800000 {
> > + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
> > + no-map;
> > + };
> > + };
> > +
> > + reg_3v3: regulator-3v3 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "On-module +V3.3";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-always-on;
> > + regulator-boot-on;
> > + };
> > +
> > + reg_1v8: regulator-1v8 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "On-module +V1.8";
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + vin-supply = <®_3v3>;
> > + regulator-always-on;
> > + regulator-boot-on;
> > + };
> > +
> > + reg_3v3_phy: regulator-3v3-phy {
> > + compatible = "regulator-fixed";
> > + regulator-name = "On-module +V3.3_PHY";
> > + gpios = <&main_gpio0 45 GPIO_ACTIVE_HIGH>;
> > + enable-active-high;
> > + regulator-always-on;
> > + };
> > +};
> > +
> > +&cpsw3g {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_rgmii1>;
> > +};
> > +
> > +&cpsw3g_mdio {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_mdio1>;
> > + status = "okay";
> > +
> > + cpsw3g_phy0: ethernet-phy@4 {
> > + compatible = "ethernet-phy-id0283.bc30";
> > + reg = <4>;
> > + reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>;
> > + reset-assert-us = <10000>;
> > + reset-deassert-us = <100000>;
> > + };
> > +};
> > +
> > +&cpsw_port1 {
> > + /*
> > + * The required RGMII TX and RX 2ns delays are implemented directly
> > + * in hardware via passive delay elements on the SOM PCB.
> > + * No delay configuration is needed in software via PHY driver.
> > + */
> > + phy-mode = "rgmii";
> > + phy-handle = <&cpsw3g_phy0>;
> > + status = "okay";
> > +};
> > +
> > +&main_i2c2 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_i2c2>;
> > + clock-frequency = <400000>;
> > + status = "okay";
> > +};
> > +
> > +&main_i2c3 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_i2c3>;
> > + clock-frequency = <400000>;
> > + status = "okay";
> > +};
> > +
> > +&main_pmx0 {
> > + pinctrl_mmc_pwrseq: main-emmc-pwrseq-pins {
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (AB23) VOUT0_DATA4.GPIO0_49 */
> > + >;
> > + };
> > +
> > + pinctrl_i2c2: main-i2c2-default-pins {
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (T22) GPMC0_CSn2.I2C2_SCL */
> > + AM62PX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (U25) GPMC0_CSn3.I2C2_SDA */
> > + >;
> > + };
> > +
> > + pinctrl_i2c3: main-i2c3-default-pins {
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A23) UART0_CTSn.I2C3_SCL */
> > + AM62PX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (C22) UART0_RTSn.I2C3_SDA */
> > + >;
> > + };
> > +
> > + pinctrl_mdio1: main-mdio1-default-pins {
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */
> > + AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */
> > + >;
> > + };
> > +
> > + pinctrl_mmc2: main-mmc2-default-pins {
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x0120, PIN_INPUT_PULLUP, 0) /* (K24) MMC2_CMD */
> > + AM62PX_IOPAD(0x0118, PIN_INPUT_PULLDOWN, 0) /* (K21) MMC2_CLK */
> > + AM62PX_IOPAD(0x011c, PIN_INPUT_PULLUP, 0) /* () MMC2_CLKLB */
> > + AM62PX_IOPAD(0x0114, PIN_INPUT_PULLUP, 0) /* (K23) MMC2_DAT0 */
> > + AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */
> > + AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */
> > + AM62PX_IOPAD(0x0108, PIN_INPUT_PULLUP, 0) /* (L21) MMC2_DAT3 */
> > + >;
> > + };
> > +
> > + pinctrl_rgmii1: main-rgmii1-default-pins {
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */
> > + AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */
> > + AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */
> > + AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */
> > + AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */
> > + AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */
> > + AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */
> > + AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */
> > + AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */
> > + AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */
> > + AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */
> > + AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */
> > + >;
> > + bootph-all;
> > + };
> > +
> > + pinctrl_spi0: main-spi0-default-pins {
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (B21) SPI0_CLK */
> > + AM62PX_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (D20) SPI0_CS0 */
> > + AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B20) SPI0_D0 */
> > + AM62PX_IOPAD(0x01c4, PIN_INPUT, 0) /* (C21) SPI0_D1 */
> > + >;
> > + };
> > +
> > + pinctrl_uart5: main-uart5-default-pins {
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x00ec, PIN_INPUT, 4) /* (AC21) VOUT0_DATA13.UART5_CTSn */
> > + AM62PX_IOPAD(0x00e8, PIN_OUTPUT, 4) /* (AD21) VOUT0_DATA12.UART5_RTSn */
> > + AM62PX_IOPAD(0x00d0, PIN_INPUT, 4) /* (AC23) VOUT0_DATA6.UART5_RXD */
> > + AM62PX_IOPAD(0x00d4, PIN_OUTPUT, 4) /* (AE23) VOUT0_DATA7.UART5_TXD */
> > + >;
> > + };
> > +
> > + pinctrl_bt: main-btgrp-pins {
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x00f4, PIN_OUTPUT, 7) /* (Y20) VOUT0_DATA15.GPIO0_60 (BT_EN) */
> > + >;
> > + };
> > +
> > + pinctrl_restouch: main-restouch-pins {
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x00c4, PIN_INPUT_PULLUP, 7) /* (Y23) VOUT0_DATA3.GPIO0_48 */
> > + >;
> > + };
> > +
> > + pinctrl_wifi: main-wifi-default-pins {
> > + pinctrl-single,pins = <
> > + AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 7) /* (AC22) VOUT0_DATA9.GPIO0_54 - WIFI_PWR_EN - */
> > + AM62PX_IOPAD(0x00f0, PIN_OUTPUT, 7) /* (AA20) VOUT0_DATA14.GPIO0_59 - WIFI_EN - */
> > + >;
> > + };
> > +};
> > +
> > +&mcu_pmx0 {
> > + pinctrl_wkup_clkout0: wkup-clkout0-default-pins {
> > + pinctrl-single,pins = <
> > + AM62PX_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */
> > + >;
> > + };
> > +};
> > +
> > +&main_spi0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_spi0>;
> > + ti,pindir-d0-out-d1-in;
> > + status = "okay";
> > +};
> > +
> > +&main_uart5 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>;
> > + uart-has-rtscts;
> > + status = "okay";
> > +
> > + bluetooth {
> > + compatible = "nxp,88w8987-bt";
> > + };
> > +};
> > +
> > +&sdhci0 {
> > + ti,driver-strength-ohm = <50>;
> > + mmc-pwrseq = <&mmc_pwrseq>;
> > + bootph-all;
> > + status = "okay";
> > +};
> > +
> > +&sdhci2 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_mmc2>, <&pinctrl_wifi>;
> > + bus-width = <4>;
> > + non-removable;
> > + keep-power-in-suspend;
> > + mmc-pwrseq = <&wifi_pwrseq>;
> > + ti,fails-without-test-cd;
> > + status = "okay";
> > +};
> > +
> > +&usbss0 {
> > + ti,vbus-divider;
> > +};
> > +
> > +&usbss1 {
> > + ti,vbus-divider;
> > +};
> > +
> > +&mailbox0_cluster0 {
> > + status = "okay";
> > +
> > + mbox_r5_0: mbox-r5-0 {
> > + ti,mbox-rx = <0 0 0>;
> > + ti,mbox-tx = <1 0 0>;
> > + };
> > +};
> > +
> > +&mailbox0_cluster1 {
> > + status = "okay";
> > +
> > + mbox_mcu_r5_0: mbox-mcu-r5-0 {
> > + ti,mbox-rx = <0 0 0>;
> > + ti,mbox-tx = <1 0 0>;
> > + };
> > +};
> > +
> > +&mcu_r5fss0 {
> > + status = "okay";
> > +};
> > +
> > +&mcu_r5fss0_core0 {
> > + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
> > + memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
> > + <&mcu_r5fss0_core0_memory_region>;
> > +};
> > +
> > +&wkup_r5fss0 {
> > + status = "okay";
> > +};
> > +
> > +&wkup_r5fss0_core0 {
> > + mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
> > + memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
> > + <&wkup_r5fss0_core0_memory_region>;
> > +};
> > +
> > +/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
> > +&mcu_gpio0 {
> > + status = "reserved";
> > +};
>
> And also drop the IPC stuff above.
>
>
> > +
> > +&mcu_gpio_intr {
> > + status = "reserved";
> > +};
> > +
> > +&wkup_rtc0 {
> > + status = "disabled";
> > +};
> > +
> > +&wkup_rti0 {
> > + /* WKUP RTI0 is used by DM firmware */
> > + status = "reserved";
> > +};
> > +
> > +&wkup_uart0 {
> > + /* WKUP UART0 is used by DM firmware */
> > + status = "reserved";
> > +};
> > +
> > +&main_uart1 {
> > + /* Main UART1 is used by TIFS firmware */
> > + status = "reserved";
> > +};
>
> And include:
>
> +#include "k3-am62p-ti-ipc-firmware.dtsi"
>
>
> so that this SOM can be left in a refactored state like all other DT.
> Of course, this means this series would have a dependency on beleswar's
> series:
> https://lore.kernel.org/linux-arm-kernel/20250905051846.1189612-1-b-padhi@ti.com/
>
> Just a suggestion here. (:
>
> ~ Judith
thank you very much for the review! That does make sense, you are right.
Would you think it makes sense to leave this refactoring for a follow‑up,
so that this series can go in without depending on Beleswar’s?
That way the patch could be merged right away, and later we include:
#include "k3-am62p-ti-ipc-firmware.dtsi"
to bring the DT in line with the others.
Just checking if that sounds reasonable to you. (:
Thanks again,
Stefano
>
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v6 2/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P
2025-09-09 6:45 ` Stefano Radaelli
@ 2025-09-09 18:35 ` Judith Mendez
0 siblings, 0 replies; 9+ messages in thread
From: Judith Mendez @ 2025-09-09 18:35 UTC (permalink / raw)
To: Stefano Radaelli
Cc: devicetree, linux-kernel, Nishanth Menon, Vignesh Raghavendra,
Tero Kristo, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-kernel
Hi Stefano,
On 9/9/25 1:45 AM, Stefano Radaelli wrote:
> Hi Judith,
>
> On Mon, Sep 08, 2025 at 01:06:45PM -0500, Judith Mendez wrote:
>> Hi Stefano,
>>
>> On 9/4/25 8:22 AM, Stefano Radaelli wrote:
>>> Add device tree support for the Variscite VAR-SOM-AM62P system on module.
>>> This SOM is designed to be used with various carrier boards.
>>>
>>> The module includes:
>>> - AM62P Sitara MPU processor
>>> - Up to 8GB of DDR4-3733 memory
>>> - eMMC storage memory
>>> - PS6522430 chip as a Power Management Integrated circuit (PMIC)
>>> - Integrated 10/100/1000 Mbps Ethernet Transceiver Analog Devices ADIN1300
>>> - Resistive touch panel interface controller TI TSC2046
>>> - I2C interfaces
>>>
>>> Only SOM-specific peripherals are enabled by default. Carrier board
>>> specific interfaces are left disabled to be enabled in the respective
>>> carrier board device trees.
>>>
>>> Link: https://www.variscite.it/product/system-on-module-som/cortex-a53-krait/var-som-am62p-ti-sitara-am62px/
>>>
>>> Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
>>> ---
>>> v6:
>>> - Removed unnecessary sdhci properties
>>> v5:
>>> - Update to match up with coding guidelines for device tree
>>> v4:
>>> - Moved every MCUs-related node into the SOM dtsi
>>> - Removed unused audio node
>>> v3:
>>> - Change compatible string to match existing mainline format
>>> - Lower case hex digits
>>> - Generic node names
>>> v2:
>>> - Fixed warnings and cleanup
>>>
>>> arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 385 ++++++++++++++++++
>>> 1 file changed, 385 insertions(+)
>>> create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
>>> new file mode 100644
>>> index 000000000000..da037993574f
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
>>> @@ -0,0 +1,385 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Common dtsi for Variscite VAR-SOM-AM62P
>>> + *
>>> + * Link: https://www.variscite.com/product/system-on-module-som/cortex-a53-krait/var-som-am62p-ti-sitara-am62px/
>>> + *
>>> + * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
>>> + *
>>> + */
>>> +
>>> +/dts-v1/;
>>> +
>>> +#include <dt-bindings/gpio/gpio.h>
>>> +#include <dt-bindings/input/input.h>
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +#include <dt-bindings/leds/common.h>
>>> +#include <dt-bindings/pwm/pwm.h>
>>> +#include "k3-am62p5.dtsi"
>>> +
>>> +/ {
>>> + compatible = "variscite,var-som-am62p", "ti,am62p5";
>>> +
>>> + wifi_pwrseq: wifi-pwrseq {
>>> + compatible = "mmc-pwrseq-simple";
>>> + post-power-on-delay-ms = <100>;
>>> + power-off-delay-us = <10000>;
>>> + reset-gpios = <&main_gpio0 54 GPIO_ACTIVE_LOW>, /* WIFI_PWR_EN */
>>> + <&main_gpio0 59 GPIO_ACTIVE_LOW>; /* WIFI_EN */
>>> + };
>>> +
>>> + mmc_pwrseq: mmc-pwrseq {
>>> + compatible = "mmc-pwrseq-emmc";
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_mmc_pwrseq>;
>>> + reset-gpios = <&main_gpio0 49 GPIO_ACTIVE_LOW>;
>>> + };
>>> +
>>> + memory@80000000 {
>>> + /* 8G RAM */
>>> + reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
>>> + <0x00000008 0x80000000 0x00000001 0x80000000>;
>>> + device_type = "memory";
>>> + bootph-pre-ram;
>>> + };
>>> +
>>> + opp-table {
>>> + /* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */
>>> + opp-1400000000 {
>>> + opp-hz = /bits/ 64 <1400000000>;
>>> + opp-supported-hw = <0x01 0x0004>;
>>> + clock-latency-ns = <6000000>;
>>> + };
>>> + };
>>> +
>>> + reserved_memory: reserved-memory {
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + ranges;
>>> +
>>> + rtos_ipc_memory_region: rtos-ipc-memory@9b500000 {
>>> + compatible = "shared-dma-pool";
>>> + reg = <0x00 0x9b500000 0x00 0x00300000>;
>>> + no-map;
>>> + };
>>> +
>>> + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 {
>>> + compatible = "shared-dma-pool";
>>> + reg = <0x00 0x9b800000 0x00 0x00100000>;
>>> + no-map;
>>> + };
>>> +
>>> + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 {
>>> + compatible = "shared-dma-pool";
>>> + reg = <0x00 0x9b900000 0x00 0x00f00000>;
>>> + no-map;
>>> + };
>>
>> Perhaps it will be a good idea to do the same refactoring as this:
>>
>> https://lore.kernel.org/linux-arm-kernel/20250905051846.1189612-30-b-padhi@ti.com/
>>
>> Meaning we drop the memory carve-outs for MCU R5SS here.
>>
>>
>>> +
>>> + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 {
>>> + compatible = "shared-dma-pool";
>>> + reg = <0x00 0x9c800000 0x00 0x00100000>;
>>> + no-map;
>>> + };
>>> +
>>> + wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 {
>>> + compatible = "shared-dma-pool";
>>> + reg = <0x00 0x9c900000 0x00 0x01e00000>;
>>> + no-map;
>>> + };
>>> +
>>> + secure_tfa_ddr: tfa@9e780000 {
>>> + reg = <0x00 0x9e780000 0x00 0x80000>;
>>> + no-map;
>>> + };
>>> +
>>> + secure_ddr: optee@9e800000 {
>>> + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
>>> + no-map;
>>> + };
>>> + };
>>> +
>>> + reg_3v3: regulator-3v3 {
>>> + compatible = "regulator-fixed";
>>> + regulator-name = "On-module +V3.3";
>>> + regulator-min-microvolt = <3300000>;
>>> + regulator-max-microvolt = <3300000>;
>>> + regulator-always-on;
>>> + regulator-boot-on;
>>> + };
>>> +
>>> + reg_1v8: regulator-1v8 {
>>> + compatible = "regulator-fixed";
>>> + regulator-name = "On-module +V1.8";
>>> + regulator-min-microvolt = <1800000>;
>>> + regulator-max-microvolt = <1800000>;
>>> + vin-supply = <®_3v3>;
>>> + regulator-always-on;
>>> + regulator-boot-on;
>>> + };
>>> +
>>> + reg_3v3_phy: regulator-3v3-phy {
>>> + compatible = "regulator-fixed";
>>> + regulator-name = "On-module +V3.3_PHY";
>>> + gpios = <&main_gpio0 45 GPIO_ACTIVE_HIGH>;
>>> + enable-active-high;
>>> + regulator-always-on;
>>> + };
>>> +};
>>> +
>>> +&cpsw3g {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_rgmii1>;
>>> +};
>>> +
>>> +&cpsw3g_mdio {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_mdio1>;
>>> + status = "okay";
>>> +
>>> + cpsw3g_phy0: ethernet-phy@4 {
>>> + compatible = "ethernet-phy-id0283.bc30";
>>> + reg = <4>;
>>> + reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>;
>>> + reset-assert-us = <10000>;
>>> + reset-deassert-us = <100000>;
>>> + };
>>> +};
>>> +
>>> +&cpsw_port1 {
>>> + /*
>>> + * The required RGMII TX and RX 2ns delays are implemented directly
>>> + * in hardware via passive delay elements on the SOM PCB.
>>> + * No delay configuration is needed in software via PHY driver.
>>> + */
>>> + phy-mode = "rgmii";
>>> + phy-handle = <&cpsw3g_phy0>;
>>> + status = "okay";
>>> +};
>>> +
>>> +&main_i2c2 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_i2c2>;
>>> + clock-frequency = <400000>;
>>> + status = "okay";
>>> +};
>>> +
>>> +&main_i2c3 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_i2c3>;
>>> + clock-frequency = <400000>;
>>> + status = "okay";
>>> +};
>>> +
>>> +&main_pmx0 {
>>> + pinctrl_mmc_pwrseq: main-emmc-pwrseq-pins {
>>> + pinctrl-single,pins = <
>>> + AM62PX_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (AB23) VOUT0_DATA4.GPIO0_49 */
>>> + >;
>>> + };
>>> +
>>> + pinctrl_i2c2: main-i2c2-default-pins {
>>> + pinctrl-single,pins = <
>>> + AM62PX_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (T22) GPMC0_CSn2.I2C2_SCL */
>>> + AM62PX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (U25) GPMC0_CSn3.I2C2_SDA */
>>> + >;
>>> + };
>>> +
>>> + pinctrl_i2c3: main-i2c3-default-pins {
>>> + pinctrl-single,pins = <
>>> + AM62PX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A23) UART0_CTSn.I2C3_SCL */
>>> + AM62PX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (C22) UART0_RTSn.I2C3_SDA */
>>> + >;
>>> + };
>>> +
>>> + pinctrl_mdio1: main-mdio1-default-pins {
>>> + pinctrl-single,pins = <
>>> + AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */
>>> + AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */
>>> + >;
>>> + };
>>> +
>>> + pinctrl_mmc2: main-mmc2-default-pins {
>>> + pinctrl-single,pins = <
>>> + AM62PX_IOPAD(0x0120, PIN_INPUT_PULLUP, 0) /* (K24) MMC2_CMD */
>>> + AM62PX_IOPAD(0x0118, PIN_INPUT_PULLDOWN, 0) /* (K21) MMC2_CLK */
>>> + AM62PX_IOPAD(0x011c, PIN_INPUT_PULLUP, 0) /* () MMC2_CLKLB */
>>> + AM62PX_IOPAD(0x0114, PIN_INPUT_PULLUP, 0) /* (K23) MMC2_DAT0 */
>>> + AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */
>>> + AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */
>>> + AM62PX_IOPAD(0x0108, PIN_INPUT_PULLUP, 0) /* (L21) MMC2_DAT3 */
>>> + >;
>>> + };
>>> +
>>> + pinctrl_rgmii1: main-rgmii1-default-pins {
>>> + pinctrl-single,pins = <
>>> + AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */
>>> + AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */
>>> + AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */
>>> + AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */
>>> + AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */
>>> + AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */
>>> + AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */
>>> + AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */
>>> + AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */
>>> + AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */
>>> + AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */
>>> + AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */
>>> + >;
>>> + bootph-all;
>>> + };
>>> +
>>> + pinctrl_spi0: main-spi0-default-pins {
>>> + pinctrl-single,pins = <
>>> + AM62PX_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (B21) SPI0_CLK */
>>> + AM62PX_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (D20) SPI0_CS0 */
>>> + AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B20) SPI0_D0 */
>>> + AM62PX_IOPAD(0x01c4, PIN_INPUT, 0) /* (C21) SPI0_D1 */
>>> + >;
>>> + };
>>> +
>>> + pinctrl_uart5: main-uart5-default-pins {
>>> + pinctrl-single,pins = <
>>> + AM62PX_IOPAD(0x00ec, PIN_INPUT, 4) /* (AC21) VOUT0_DATA13.UART5_CTSn */
>>> + AM62PX_IOPAD(0x00e8, PIN_OUTPUT, 4) /* (AD21) VOUT0_DATA12.UART5_RTSn */
>>> + AM62PX_IOPAD(0x00d0, PIN_INPUT, 4) /* (AC23) VOUT0_DATA6.UART5_RXD */
>>> + AM62PX_IOPAD(0x00d4, PIN_OUTPUT, 4) /* (AE23) VOUT0_DATA7.UART5_TXD */
>>> + >;
>>> + };
>>> +
>>> + pinctrl_bt: main-btgrp-pins {
>>> + pinctrl-single,pins = <
>>> + AM62PX_IOPAD(0x00f4, PIN_OUTPUT, 7) /* (Y20) VOUT0_DATA15.GPIO0_60 (BT_EN) */
>>> + >;
>>> + };
>>> +
>>> + pinctrl_restouch: main-restouch-pins {
>>> + pinctrl-single,pins = <
>>> + AM62PX_IOPAD(0x00c4, PIN_INPUT_PULLUP, 7) /* (Y23) VOUT0_DATA3.GPIO0_48 */
>>> + >;
>>> + };
>>> +
>>> + pinctrl_wifi: main-wifi-default-pins {
>>> + pinctrl-single,pins = <
>>> + AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 7) /* (AC22) VOUT0_DATA9.GPIO0_54 - WIFI_PWR_EN - */
>>> + AM62PX_IOPAD(0x00f0, PIN_OUTPUT, 7) /* (AA20) VOUT0_DATA14.GPIO0_59 - WIFI_EN - */
>>> + >;
>>> + };
>>> +};
>>> +
>>> +&mcu_pmx0 {
>>> + pinctrl_wkup_clkout0: wkup-clkout0-default-pins {
>>> + pinctrl-single,pins = <
>>> + AM62PX_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */
>>> + >;
>>> + };
>>> +};
>>> +
>>> +&main_spi0 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_spi0>;
>>> + ti,pindir-d0-out-d1-in;
>>> + status = "okay";
>>> +};
>>> +
>>> +&main_uart5 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>;
>>> + uart-has-rtscts;
>>> + status = "okay";
>>> +
>>> + bluetooth {
>>> + compatible = "nxp,88w8987-bt";
>>> + };
>>> +};
>>> +
>>> +&sdhci0 {
>>> + ti,driver-strength-ohm = <50>;
>>> + mmc-pwrseq = <&mmc_pwrseq>;
>>> + bootph-all;
>>> + status = "okay";
>>> +};
>>> +
>>> +&sdhci2 {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&pinctrl_mmc2>, <&pinctrl_wifi>;
>>> + bus-width = <4>;
>>> + non-removable;
>>> + keep-power-in-suspend;
>>> + mmc-pwrseq = <&wifi_pwrseq>;
>>> + ti,fails-without-test-cd;
>>> + status = "okay";
>>> +};
>>> +
>>> +&usbss0 {
>>> + ti,vbus-divider;
>>> +};
>>> +
>>> +&usbss1 {
>>> + ti,vbus-divider;
>>> +};
>>> +
>>> +&mailbox0_cluster0 {
>>> + status = "okay";
>>> +
>>> + mbox_r5_0: mbox-r5-0 {
>>> + ti,mbox-rx = <0 0 0>;
>>> + ti,mbox-tx = <1 0 0>;
>>> + };
>>> +};
>>> +
>>> +&mailbox0_cluster1 {
>>> + status = "okay";
>>> +
>>> + mbox_mcu_r5_0: mbox-mcu-r5-0 {
>>> + ti,mbox-rx = <0 0 0>;
>>> + ti,mbox-tx = <1 0 0>;
>>> + };
>>> +};
>>> +
>>> +&mcu_r5fss0 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&mcu_r5fss0_core0 {
>>> + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>;
>>> + memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
>>> + <&mcu_r5fss0_core0_memory_region>;
>>> +};
>>> +
>>> +&wkup_r5fss0 {
>>> + status = "okay";
>>> +};
>>> +
>>> +&wkup_r5fss0_core0 {
>>> + mboxes = <&mailbox0_cluster0 &mbox_r5_0>;
>>> + memory-region = <&wkup_r5fss0_core0_dma_memory_region>,
>>> + <&wkup_r5fss0_core0_memory_region>;
>>> +};
>>> +
>>> +/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
>>> +&mcu_gpio0 {
>>> + status = "reserved";
>>> +};
>>
>> And also drop the IPC stuff above.
>>
>>
>>> +
>>> +&mcu_gpio_intr {
>>> + status = "reserved";
>>> +};
>>> +
>>> +&wkup_rtc0 {
>>> + status = "disabled";
>>> +};
>>> +
>>> +&wkup_rti0 {
>>> + /* WKUP RTI0 is used by DM firmware */
>>> + status = "reserved";
>>> +};
>>> +
>>> +&wkup_uart0 {
>>> + /* WKUP UART0 is used by DM firmware */
>>> + status = "reserved";
>>> +};
>>> +
>>> +&main_uart1 {
>>> + /* Main UART1 is used by TIFS firmware */
>>> + status = "reserved";
>>> +};
>>
>> And include:
>>
>> +#include "k3-am62p-ti-ipc-firmware.dtsi"
>>
>>
>> so that this SOM can be left in a refactored state like all other DT.
>> Of course, this means this series would have a dependency on beleswar's
>> series:
>> https://lore.kernel.org/linux-arm-kernel/20250905051846.1189612-1-b-padhi@ti.com/
>>
>> Just a suggestion here. (:
>>
>> ~ Judith
>
> thank you very much for the review! That does make sense, you are right.
>
> Would you think it makes sense to leave this refactoring for a follow‑up,
> so that this series can go in without depending on Beleswar’s?
> That way the patch could be merged right away, and later we include:
>
> #include "k3-am62p-ti-ipc-firmware.dtsi"
>
> to bring the DT in line with the others.
>
> Just checking if that sounds reasonable to you. (:
No Problem (:
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v6 0/3] Add support for Variscite VAR-SOM-AM62P5 and Symphony board
2025-09-04 13:22 [PATCH v6 0/3] Add support for Variscite VAR-SOM-AM62P5 and Symphony board Stefano Radaelli
` (2 preceding siblings ...)
2025-09-04 13:22 ` [PATCH v6 3/3] arm64: dts: ti: var-som-am62p: Add support for Variscite Symphony Board Stefano Radaelli
@ 2025-09-09 18:37 ` Judith Mendez
3 siblings, 0 replies; 9+ messages in thread
From: Judith Mendez @ 2025-09-09 18:37 UTC (permalink / raw)
To: Stefano Radaelli, devicetree, linux-kernel
Cc: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-kernel
Hi,
On 9/4/25 8:22 AM, Stefano Radaelli wrote:
> This patch series adds support for the Variscite VAR-SOM-AM62P system on module
> and the Symphony carrier board.
>
> The VAR-SOM-AM62P is a compact SOM based on the TI AM62P Sitara processor,
> featuring up to 8GB DDR4 memory, eMMC storage, Gigabit Ethernet, and various
> peripheral interfaces. The Symphony board is a feature-rich carrier board that
> showcases the SOM capabilities.
>
> The series includes:
> - Device tree bindings documentation
> - SOM device tree with common peripherals
> - Symphony carrier board device tree with board-specific features
>
> The implementation follows the standard SOM + carrier board pattern where the
> SOM dtsi contains only peripherals mounted on the module, while carrier-specific
> interfaces are enabled in the board dts.
>
> Tested on VAR-SOM-AM62P with Symphony carrier board.
For the series,
Reviewed-by: Judith Mendez <jm@ti.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2025-09-09 18:38 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-09-04 13:22 [PATCH v6 0/3] Add support for Variscite VAR-SOM-AM62P5 and Symphony board Stefano Radaelli
2025-09-04 13:22 ` [PATCH v6 1/3] dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62P Stefano Radaelli
2025-09-04 13:22 ` [PATCH v6 2/3] arm64: dts: ti: Add support " Stefano Radaelli
2025-09-08 18:06 ` Judith Mendez
2025-09-09 6:45 ` Stefano Radaelli
2025-09-09 18:35 ` Judith Mendez
2025-09-08 18:09 ` Judith Mendez
2025-09-04 13:22 ` [PATCH v6 3/3] arm64: dts: ti: var-som-am62p: Add support for Variscite Symphony Board Stefano Radaelli
2025-09-09 18:37 ` [PATCH v6 0/3] Add support for Variscite VAR-SOM-AM62P5 and Symphony board Judith Mendez
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