From: Will Deacon <will@kernel.org>
To: Sudeep Holla <sudeep.holla@arm.com>
Cc: Yicong Yang <yangyicong@huawei.com>,
mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org,
james.clark@linaro.org, robh@kernel.org,
anshuman.khandual@arm.com, jonathan.cameron@huawei.com,
hejunhao3@huawei.com, linuxarm@huawei.com,
prime.zeng@hisilicon.com, xuwei5@huawei.com,
wangyushan12@huawei.com, yangyicong@hisilicon.com
Subject: Re: [PATCH v2 2/2] perf: arm_pmuv3: Don't use PMCCNTR_EL0 on SMT cores
Date: Fri, 19 Sep 2025 12:18:45 +0100 [thread overview]
Message-ID: <aM08FXtLJbiR4ttw@willie-the-truck> (raw)
In-Reply-To: <20250919-tidy-authentic-slug-f325dc@sudeepholla>
On Fri, Sep 19, 2025 at 10:37:45AM +0100, Sudeep Holla wrote:
> On Thu, Sep 18, 2025 at 02:32:20PM +0100, Will Deacon wrote:
> > On Wed, Aug 20, 2025 at 04:45:34PM +0800, Yicong Yang wrote:
> > > diff --git a/include/linux/arch_topology.h b/include/linux/arch_topology.h
> > > index d72d6e5aa200..daa1af2e8204 100644
> > > --- a/include/linux/arch_topology.h
> > > +++ b/include/linux/arch_topology.h
> > > @@ -89,6 +89,17 @@ void remove_cpu_topology(unsigned int cpuid);
> > > void reset_cpu_topology(void);
> > > int parse_acpi_topology(void);
> > > void freq_inv_set_max_ratio(int cpu, u64 max_rate);
> > > +
> > > +/*
> > > + * Architectures like ARM64 don't have reliable architectural way to get SMT
> > > + * information and depend on the firmware (ACPI/OF) report. Non-SMT core won't
> > > + * initialize thread_id so we can use this to detect the SMT implementation.
> > > + */
> > > +static inline bool topology_core_has_smt(int cpu)
> > > +{
> > > + return cpu_topology[cpu].thread_id != -1;
> > > +}
> >
> > Sudeep -- is this ok?
> >
>
> Yes, this looks correct as the topology_sibling_cpumask(aka thread_sibling
> mask) changes with hotplug events and may not be desirable. Not sure if we
> can do any better with name in case we need to check for active/online thread
> sibling in the future(I assuming it is for sure not needed here).
Great, thanks for confirming. We're just using this to figure out whether
the hardware implements SMT so I don't think we care about the thread status
at all.
Will
next prev parent reply other threads:[~2025-09-19 11:19 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-20 8:45 [PATCH v2 0/2] perf: arm_pmuv3: Don't use PMCCNTR_EL0 on SMT cores Yicong Yang
2025-08-20 8:45 ` [PATCH v2 1/2] perf: arm_pmuv3: Factor out PMCCNTR_EL0 use conditions Yicong Yang
2025-08-20 8:45 ` [PATCH v2 2/2] perf: arm_pmuv3: Don't use PMCCNTR_EL0 on SMT cores Yicong Yang
2025-09-18 13:32 ` Will Deacon
2025-09-19 8:56 ` Yicong Yang
2025-09-19 9:16 ` Mark Rutland
2025-09-19 10:27 ` Yicong Yang
2025-09-19 11:17 ` Will Deacon
2025-09-19 9:37 ` Sudeep Holla
2025-09-19 11:18 ` Will Deacon [this message]
2025-09-08 7:09 ` [PATCH v2 0/2] " Yicong Yang
2025-09-18 16:43 ` Will Deacon
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