From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B883CA0FED for ; Wed, 10 Sep 2025 14:14:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:In-Reply-To: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=4AKBrsHYyZy6NVWerxVC8iAlV9/6fvAVIrP6ESd120U=; b=YjnG4nn1sJO5IJUigbaOx+B/Vc LPDrDatsSXUnQuKFu4N3SpTE++5iCzvGIlDHO/+HaHWCEmVqjPnpKh4pOQ2ePnVo1z8sg1QuwGhQz mQhjjnpBTBWte/fO5+7NXIKiuqfvMH/lEAX93G6M+/yEXHIuW4A7qSPj40NkKN2WV39/R47+ezg4r 6SxppIOk0Lj3ydw6zWwYypnLj2lknkPjyqaO3pYqtSs/oyYSre5h11svBsXeu47S5TpfliLJBpJWZ BYarkm+5LeSRXH1Vvkn7OUFnMbFMtD2fD6H/mp2MvdvZPkFBqQBvvOUU0E04DJJv3q6jSSGan12LM wv+/SIZg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uwLaj-0000000EdBY-1lCI; Wed, 10 Sep 2025 14:14:33 +0000 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uwLaf-0000000Ed8w-3zTH for linux-arm-kernel@lists.infradead.org; Wed, 10 Sep 2025 14:14:31 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1757513667; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=4AKBrsHYyZy6NVWerxVC8iAlV9/6fvAVIrP6ESd120U=; b=BTxWaaHTtOtGwDywzanXaVXZxJdaVxryrkLrnQ4nhGLAgnTTwY3Q9tNVf3ENMSRMrSTIZ0 bSR3yWws/GO+q7PDyXpBN4UNskvGRVV3vsPhIgcPJ4fcM9EQeHzdOfOxqhTphP01qIz+78 K8MmIXLWbpmTIuOnQbY0Q0ku5vJONMA= Received: from mail-qk1-f200.google.com (mail-qk1-f200.google.com [209.85.222.200]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-186-EsLPFOA7Mt6saJN19CZ2-Q-1; Wed, 10 Sep 2025 10:14:25 -0400 X-MC-Unique: EsLPFOA7Mt6saJN19CZ2-Q-1 X-Mimecast-MFC-AGG-ID: EsLPFOA7Mt6saJN19CZ2-Q_1757513665 Received: by mail-qk1-f200.google.com with SMTP id af79cd13be357-81b8d38504fso727430685a.3 for ; Wed, 10 Sep 2025 07:14:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757513665; x=1758118465; h=user-agent:in-reply-to:content-disposition:mime-version:references :message-id:subject:cc:to:from:date:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4AKBrsHYyZy6NVWerxVC8iAlV9/6fvAVIrP6ESd120U=; b=MLVA/NJWW1h/zJNoGuBTI1G69k8BCsSma1B5+z07YHs2mCX05kN6wZZmxPmC4P+5of wveTs5l9L9dZ3UF9wzP+d65C6vx8d4CWrk5xtberBnBOwOfVOZklsH48MSTpGmsKmWUN 0kGy6qPekK1fKq+LsdlHxH5F9y4AxGW9SxVNnHqZMrbJxKfu8vZAmRhOfmNzD6kQZGoo EzCwAwGyNLkmWeffAAP0RUKr6o9FPqfZ8xfYsV1m4GMee+oTaKg3RugOJcqsu0OOzaIV qX9Kx6tpwMM0K/wFNIHRbiVJRDj/jWNtoqGz+/PCbWQXALdHXHo34Ej4NtXB8ODC9KyY RTlQ== X-Forwarded-Encrypted: i=1; AJvYcCVccfuNM8/obTbGibMqnFsIN1ZEaj4N3MJXXIRdQlXm3jmn2NHoldPXwGyI/eCtv3EU4uCKYYdktkKRygCL50yt@lists.infradead.org X-Gm-Message-State: AOJu0YzSRxdVT4SfDTV0Rq47yKo4pHiORrEyxVe5WfJPfIvpsqu7I4Bm 5XmDbAZA27/TKrU54PL3wEO17Aei/CzeRVgcLOnXVDaq093lMzK5XxP7SaIENdQ5AF/eqQhxKcH ttg3rdtg12UjTv+usJvh6cM5IHKfcVh+T4gu8JXzzwUwDrh88xPGSxlYFarF+yxLYiG58Ys3b7+ k6 X-Gm-Gg: ASbGnctu8C60ov7lVNvTkiH2T6hUTVnsTH4VnxsfAySMylS6pRM7hEbgvSSveeIZEhj LgrB1IHK7LLVrAbPTb1t/QV5yt171WwknjCsEnh1tdtx71Mnjb2S6Q3vTwJosbAiBMhUBAhCWkN Cjb9cCtte+bu5YM6H0fqeBGMa9+uqSmpkV4WcIq1XYTdhYw7vCuBk5bFy+6t0Fc+sRALVpM/6B+ zG2gORg8UMrGdKtYvANvQ5dztSf1eyQ87t/9q2l4ZkX9n9WRTfngPJOwxR2DLDFcf/B9wWxGUwz ENzCx4fg/Yh4aV+k29gwIQRx8bVQjyU6eMt+Pz8s9yRvlMnJP1ji4pCiSlc2SBJJKlelV6FMnJy vbTnUzIj2lhrVttiVPgQ= X-Received: by 2002:a05:620a:1997:b0:7e8:922:f02b with SMTP id af79cd13be357-813bed042c0mr1615333185a.25.1757513665031; Wed, 10 Sep 2025 07:14:25 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFkFeL3wPJOKIe3shUG9pzAQKQjdBD+pGyVy/83wrA05r4tPdXbaw2hUPMEXQ3KZIEvXGTTLQ== X-Received: by 2002:a05:620a:1997:b0:7e8:922:f02b with SMTP id af79cd13be357-813bed042c0mr1615324385a.25.1757513664239; Wed, 10 Sep 2025 07:14:24 -0700 (PDT) Received: from x1 (c-73-183-52-120.hsd1.pa.comcast.net. [73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-81b58b5d7fesm299937185a.8.2025.09.10.07.14.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Sep 2025 07:14:23 -0700 (PDT) Date: Wed, 10 Sep 2025 10:14:20 -0400 From: Brian Masney To: Ryan Chen Cc: Michael Turquette , Stephen Boyd , Philipp Zabel , Joel Stanley , Andrew Jeffery , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mo Elbadry , Rom Lemarchand , William Kennington , Yuxiao Zhang , wthai@nvidia.com, leohu@nvidia.com, dkodihalli@nvidia.com, spuranik@nvidia.com Subject: Re: [PATCH v12 3/3] clk: aspeed: add AST2700 clock driver Message-ID: References: <20250708052909.4145983-1-ryan_chen@aspeedtech.com> <20250708052909.4145983-4-ryan_chen@aspeedtech.com> MIME-Version: 1.0 In-Reply-To: <20250708052909.4145983-4-ryan_chen@aspeedtech.com> User-Agent: Mutt/2.2.14 (2025-02-20) X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: Ht_WGMYp9J73C3uSGRlYdkodLUdTEaSNthc3mBRrHfs_1757513665 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250910_071430_062452_6AE581D5 X-CRM114-Status: GOOD ( 22.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Ryan, On Tue, Jul 08, 2025 at 01:29:09PM +0800, Ryan Chen wrote: > Add AST2700 clock controller driver and also use axiliary > device framework register the reset controller driver. > Due to clock and reset using the same register region. > > Signed-off-by: Ryan Chen I just have a few very minor style comments below. Otherwise the driver looks good to me. > +static struct clk_hw *ast2700_clk_hw_register_hpll(void __iomem *reg, > + const char *name, const char *parent_name, > + struct ast2700_clk_ctrl *clk_ctrl) > +{ > + unsigned int mult, div; > + u32 val; > + > + val = readl(clk_ctrl->base + SCU0_HWSTRAP1); > + if ((readl(clk_ctrl->base) & REVISION_ID) && (val & BIT(3))) { > + switch ((val & GENMASK(4, 2)) >> 2) { > + case 2: > + return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name, NULL, > + 0, 1800 * HZ_PER_MHZ); > + case 3: > + return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name, NULL, > + 0, 1700 * HZ_PER_MHZ); > + case 6: > + return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name, NULL, > + 0, 1200 * HZ_PER_MHZ); > + case 7: > + return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name, NULL, > + 0, 800 * HZ_PER_MHZ); > + default: > + return ERR_PTR(-EINVAL); > + } > + } else if ((val & GENMASK(3, 2)) != 0) { > + switch ((val & GENMASK(3, 2)) >> 2) { > + case 1: > + return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name, NULL, > + 0, 1900 * HZ_PER_MHZ); > + case 2: > + return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name, NULL, > + 0, 1800 * HZ_PER_MHZ); > + case 3: > + return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name, NULL, > + 0, 1700 * HZ_PER_MHZ); > + default: > + return ERR_PTR(-EINVAL); > + } > + } else { > + val = readl(reg); > + > + if (val & BIT(24)) { > + /* Pass through mode */ > + mult = 1; > + div = 1; > + } else { > + u32 m = val & 0x1fff; > + u32 n = (val >> 13) & 0x3f; > + u32 p = (val >> 19) & 0xf; > + > + mult = (m + 1) / (2 * (n + 1)); > + div = (p + 1); The ( ) is unnecessary here. > + } > + } > + > + return devm_clk_hw_register_fixed_factor(clk_ctrl->dev, name, parent_name, 0, mult, div); > +} > + > +static struct clk_hw *ast2700_clk_hw_register_pll(int clk_idx, void __iomem *reg, > + const char *name, const char *parent_name, > + struct ast2700_clk_ctrl *clk_ctrl) > +{ > + int scu = clk_ctrl->clk_data->scu; > + unsigned int mult, div; > + u32 val = readl(reg); > + > + if (val & BIT(24)) { > + /* Pass through mode */ > + mult = 1; > + div = 1; > + } else { > + u32 m = val & 0x1fff; > + u32 n = (val >> 13) & 0x3f; > + u32 p = (val >> 19) & 0xf; > + > + if (scu) { > + mult = (m + 1) / (n + 1); > + div = (p + 1); > + } else { > + if (clk_idx == SCU0_CLK_MPLL) { > + mult = m / (n + 1); > + div = (p + 1); > + } else { > + mult = (m + 1) / (2 * (n + 1)); > + div = (p + 1); The ( ) is unnecessary on div on the three places above. > +static void ast2700_soc1_configure_i3c_clk(struct ast2700_clk_ctrl *clk_ctrl) > +{ > + if (readl(clk_ctrl->base + SCU1_REVISION_ID) & REVISION_ID) > + /* I3C 250MHz = HPLL/4 */ > + writel((readl(clk_ctrl->base + SCU1_CLK_SEL2) & > + ~SCU1_CLK_I3C_DIV_MASK) | > + FIELD_PREP(SCU1_CLK_I3C_DIV_MASK, > + SCU1_CLK_I3C_DIV(4)), > + clk_ctrl->base + SCU1_CLK_SEL2); This block is hard to read. What do you think about this instead? if (readl(clk_ctrl->base + SCU1_REVISION_ID) & REVISION_ID) { u32 val; /* I3C 250MHz = HPLL/4 */ val = readl(clk_ctrl->base + SCU1_CLK_SEL2) & ~SCU1_CLK_I3C_DIV_MASK; val |= FIELD_PREP(SCU1_CLK_I3C_DIV_MASK, SCU1_CLK_I3C_DIV(4)); writel(val, clk_ctrl->base + SCU1_CLK_SEL2); } With those addressed: Reviewed-by: Brian Masney