From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7484FCA1013 for ; Thu, 18 Sep 2025 15:19:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=3xhhxlrbbCxkzbwy8FbRQs0Th0Q0Jlv1xluCDf7EaA4=; b=b/4fvaqTSwr/nC+h4ZoreCH/6J Xq835NRVjht6hTlXFM6Kh2zl/ggHLePZ1OG0I7e+vPqTOsYMFrKX1yxC1GeQUd8qM/wNt7DUAoOri Gp4r4uy0ZtnAdhiTD1WjRdxafgtbbIhhAOpHLDX+c/HUTBEkhYC6P7ZuvNJg8QzS5pQ1bu1NevMG/ AblVwhJYSuzH1YHsbevjPfERVv/MswyVfAG344WMPN1auODRH4xXcUsYAk6pNmNViviZQSZxHYtaV 0CHAjxcsHLB4VxmrbS4HVev1xdCwrD0E6D0fXiBDJC3BOZhiPEMBeoLTl9TnwXry6RZYP7FPTbFrV 5+g3UE+A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uzGPP-00000000KyK-2TFq; Thu, 18 Sep 2025 15:18:55 +0000 Received: from tor.source.kernel.org ([2600:3c04:e001:324:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uzGPN-00000000Kxf-42nD for linux-arm-kernel@lists.infradead.org; Thu, 18 Sep 2025 15:18:54 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 4A4F0601BC; Thu, 18 Sep 2025 15:18:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C602CC4CEE7; Thu, 18 Sep 2025 15:18:51 +0000 (UTC) Date: Thu, 18 Sep 2025 16:18:49 +0100 From: Catalin Marinas To: Ryan Roberts Cc: Will Deacon , Mark Rutland , James Morse , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH v1 2/2] arm64: tlbflush: Don't broadcast if mm was only active on local cpu Message-ID: References: <20250829153510.2401161-1-ryan.roberts@arm.com> <20250829153510.2401161-3-ryan.roberts@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250829153510.2401161-3-ryan.roberts@arm.com> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Aug 29, 2025 at 04:35:08PM +0100, Ryan Roberts wrote: > diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c > index b2ac06246327..adf4fc26ddb6 100644 > --- a/arch/arm64/mm/context.c > +++ b/arch/arm64/mm/context.c > @@ -214,9 +214,10 @@ static u64 new_context(struct mm_struct *mm) > > void check_and_switch_context(struct mm_struct *mm) > { > - unsigned long flags; > - unsigned int cpu; > + unsigned int cpu = smp_processor_id(); > u64 asid, old_active_asid; > + unsigned int active; > + unsigned long flags; > > if (system_supports_cnp()) > cpu_set_reserved_ttbr0(); > @@ -251,7 +252,6 @@ void check_and_switch_context(struct mm_struct *mm) > atomic64_set(&mm->context.id, asid); > } > > - cpu = smp_processor_id(); > if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) > local_flush_tlb_all(); > > @@ -262,6 +262,30 @@ void check_and_switch_context(struct mm_struct *mm) > > arm64_apply_bp_hardening(); > > + /* > + * Update mm->context.active_cpu in such a manner that we avoid cmpxchg > + * and dsb unless we definitely need it. If initially ACTIVE_CPU_NONE > + * then we are the first cpu to run so set it to our id. If initially > + * any id other than ours, we are the second cpu to run so set it to > + * ACTIVE_CPU_MULTIPLE. If we update the value then we must issue > + * dsb(ishst) to ensure stores to mm->context.active_cpu are ordered > + * against the TTBR0 write in cpu_switch_mm()/uaccess_enable(); the > + * store must be visible to another cpu before this cpu could have > + * populated any TLB entries based on the pgtables that will be > + * installed. > + */ > + active = READ_ONCE(mm->context.active_cpu); > + if (active != cpu && active != ACTIVE_CPU_MULTIPLE) { > + if (active == ACTIVE_CPU_NONE) > + active = cmpxchg_relaxed(&mm->context.active_cpu, > + ACTIVE_CPU_NONE, cpu); > + > + if (active != ACTIVE_CPU_NONE) > + WRITE_ONCE(mm->context.active_cpu, ACTIVE_CPU_MULTIPLE); > + > + dsb(ishst); > + } I realised when we talked earlier that we can reset active_cpu on the slow path if we got a new ASID. I think it's best to do it in new_context(). The fork() case where the child may unnecessarily inherit the parent's active_cpu is already handled by init_new_context() in this patch. -- Catalin