[PATCH v6 2/4] PCI: dwc: Don't poll L2 if QUIRK_NOL2POLL_IN_PM is existing in suspend

Richard Zhu
2025-09-24T07:24:18Z

Refer to PCIe r6.0, sec 5.2, fig 5-1 Link Power Management State Flow
Diagram. Both L0 and L2/L3 Ready can be transferred to LDn directly.

It's harmless to let dw_pcie_suspend_noirq() proceed suspend after the
PME_Turn_Off is sent out, whatever the LTSSM state is in L2 or L3 after
a recommended 10ms max wait refer to PCIe r6.0, sec 5.3.3.2.1 PME
Synchronization.

The LTSSM states are inaccessible on i.MX6QP and i.MX7D after the
PME_Turn_Off is sent out.

To support this case, don't poll L2 state and apply a simple delay of
PCIE_PME_TO_L2_TIMEOUT_US(10ms) if the QUIRK_NOL2POLL_IN_PM flag is set
in suspend.

Cc: stable@vger.kernel.org
Fixes: 4774faf854f5 ("PCI: dwc: Implement generic suspend/resume functionality")
Fixes: a528d1a72597 ("PCI: imx6: Use DWC common suspend resume method")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 4 +++
.../pci/controller/dwc/pcie-designware-host.c | 34 +++++++++++++------
drivers/pci/controller/dwc/pcie-designware.h | 4 +++
3 files changed, 32 insertions(+), 10 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 80e48746bbaf..a59b5282c3cc 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -125,6 +125,7 @@ struct imx_pcie_drvdata {
enum imx_pcie_variants variant;
enum dw_pcie_device_mode mode;
u32 flags;
+ u32 quirk;
int dbi_length;
const char *gpr;
const u32 ltssm_off;
@@ -1765,6 +1766,7 @@ static int imx_pcie_probe(struct platform_device *pdev)
if (ret)
return ret;

+ pci->quirk_flag = imx_pcie->drvdata->quirk;
pci->use_parent_dt_ranges = true;
if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) {
ret = imx_add_pcie_ep(imx_pcie, pdev);
@@ -1849,6 +1851,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.enable_ref_clk = imx6q_pcie_enable_ref_clk,
.core_reset = imx6qp_pcie_core_reset,
.ops = &imx_pcie_host_ops,
+ .quirk = QUIRK_NOL2POLL_IN_PM,
},
[IMX7D] = {
.variant = IMX7D,
@@ -1860,6 +1863,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.enable_ref_clk = imx7d_pcie_enable_ref_clk,
.core_reset = imx7d_pcie_core_reset,
+ .quirk = QUIRK_NOL2POLL_IN_PM,
},
[IMX8MQ] = {
.variant = IMX8MQ,
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 9d46d1f0334b..57a1ba08c427 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -1016,15 +1016,29 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci)
return ret;
}

- ret = read_poll_timeout(dw_pcie_get_ltssm, val,
- val == DW_PCIE_LTSSM_L2_IDLE ||
- val <= DW_PCIE_LTSSM_DETECT_WAIT,
- PCIE_PME_TO_L2_TIMEOUT_US/10,
- PCIE_PME_TO_L2_TIMEOUT_US, false, pci);
- if (ret) {
- /* Only log message when LTSSM isn't in DETECT or POLL */
- dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val);
- return ret;
+ if (dwc_quirk(pci, QUIRK_NOL2POLL_IN_PM)) {
+ /*
+ * Add the QUIRK_NOL2_POLL_IN_PM case to avoid the read hang,
+ * when LTSSM is not powered in L2/L3/LDn properly.
+ *
+ * Refer to PCIe r6.0, sec 5.2, fig 5-1 Link Power Management
+ * State Flow Diagram. Both L0 and L2/L3 Ready can be
+ * transferred to LDn directly. On the LTSSM states poll broken
+ * platforms, add a max 10ms delay refer to PCIe r6.0,
+ * sec 5.3.3.2.1 PME Synchronization.
+ */
+ mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000);
+ } else {
+ ret = read_poll_timeout(dw_pcie_get_ltssm, val,
+ val == DW_PCIE_LTSSM_L2_IDLE ||
+ val <= DW_PCIE_LTSSM_DETECT_WAIT,
+ PCIE_PME_TO_L2_TIMEOUT_US/10,
+ PCIE_PME_TO_L2_TIMEOUT_US, false, pci);
+ if (ret) {
+ /* Only log message when LTSSM isn't in DETECT or POLL */
+ dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val);
+ return ret;
+ }
}

/*
@@ -1040,7 +1054,7 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci)

pci->suspended = true;

- return ret;
+ return 0;
}
EXPORT_SYMBOL_GPL(dw_pcie_suspend_noirq);

diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 00f52d472dcd..4e5bf6cb6ce8 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -295,6 +295,9 @@
/* Default eDMA LLP memory size */
#define DMA_LLP_MEM_SIZE PAGE_SIZE

+#define QUIRK_NOL2POLL_IN_PM BIT(0)
+#define dwc_quirk(pci, val) (pci->quirk_flag & val)
+
struct dw_pcie;
struct dw_pcie_rp;
struct dw_pcie_ep;
@@ -504,6 +507,7 @@ struct dw_pcie {
const struct dw_pcie_ops *ops;
u32 version;
u32 type;
+ u32 quirk_flag;
unsigned long caps;
int num_lanes;
int max_link_speed;
--
2.37.1