From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D4F67CCA470 for ; Tue, 7 Oct 2025 15:07:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=gX8d+Gz2dOwNhseztYh7B5DGvD6YJa9caF73ncNPvB4=; b=nrtdlKMZWKlVPA59TzM+fLQthv d6VHWgb/SaO3xw5bj7RxIkGc0EhXzKi/eq87aD4h7mS91SZcguHCPsLW6XzS9lLR8DaM9x0zDXf3d 0LKtK0YM1ydxEsK+UORFVZp6C0bplvbEQnMYUJfiCoGISADpVX1gkkYV80SXyinmLQvGEvls1VV3e LRkL/tEDtw+Uqvj1argc5xPBhwzLHVbyhTqfLLsijBEgUh9XqAE1SQKqVfJXapbaLjgxccygQGHeo NaCJwT2Xy9vQgSQ4n53xV64ZWyJF8S3AYjIbrVb0Op3dOnyNpZRnthDMgqkFZd8jzdCgyGAGkutMt msVr6edg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1v69HI-00000002Fcu-10Pj; Tue, 07 Oct 2025 15:07:00 +0000 Received: from sea.source.kernel.org ([172.234.252.31]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1v69HG-00000002FcB-0Efl for linux-arm-kernel@lists.infradead.org; Tue, 07 Oct 2025 15:06:59 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 5DA8B449A6; Tue, 7 Oct 2025 15:06:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CAFC5C4CEF1; Tue, 7 Oct 2025 15:06:55 +0000 (UTC) Date: Tue, 7 Oct 2025 16:06:53 +0100 From: Catalin Marinas To: Lorenzo Pieralisi Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sascha Bischoff , Will Deacon , Mark Rutland , Marc Zyngier Subject: Re: [PATCH v2] arm64/sysreg: Fix GIC CDEOI instruction encoding Message-ID: References: <20251007102600.879337-1-lpieralisi@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251007102600.879337-1-lpieralisi@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251007_080658_113974_6CBBF75D X-CRM114-Status: GOOD ( 15.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Oct 07, 2025 at 12:26:00PM +0200, Lorenzo Pieralisi wrote: > The GIC CDEOI system instruction requires the Rt field to be set to 0b11111 > otherwise the instruction behaviour becomes CONSTRAINED UNPREDICTABLE. > > Currenly, its usage is encoded as a system register write, with a constant > 0 value: > > write_sysreg_s(0, GICV5_OP_GIC_CDEOI) > > While compiling with GCC, the 0 constant value, through these asm > constraints and modifiers ('x' modifier and 'Z' constraint combo): > > asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); > > forces the compiler to issue the XZR register for the MSR operation (ie > that corresponds to Rt == 0b11111) issuing the right instruction encoding. > > Unfortunately LLVM does not yet understand that modifier/constraint > combo so it ends up issuing a different register from XZR for the MSR > source, which in turns means that it encodes the GIC CDEOI instruction > wrongly and the instruction behaviour becomes CONSTRAINED UNPREDICTABLE > that we must prevent. > > Add a conditional to write_sysreg_s() macro that detects whether it > is passed a constant 0 value and issues an MSR write with XZR as source > register - explicitly doing what the asm modifier/constraint is meant to > achieve through constraints/modifiers, fixing the LLVM compilation issue. > > Fixes: 7ec80fb3f025 ("irqchip/gic-v5: Add GICv5 PPI support") > Suggested-by: Catalin Marinas > Signed-off-by: Lorenzo Pieralisi > Acked-by: Marc Zyngier > Cc: stable@vger.kernel.org > Cc: Sascha Bischoff > Cc: Will Deacon > Cc: Catalin Marinas > Cc: Mark Rutland > Cc: Marc Zyngier Reviewed-by: Catalin Marinas (unless Will sends another pull request before -rc1, I'll pick this patch shortly after)