Re: [PATCH v2] arm64/sysreg: Fix GIC CDEOI instruction encoding

[Will Deacon <will@kernel.org>]

On Tue, Oct 07, 2025 at 04:06:53PM +0100, Catalin Marinas wrote:
> On Tue, Oct 07, 2025 at 12:26:00PM +0200, Lorenzo Pieralisi wrote:
> > The GIC CDEOI system instruction requires the Rt field to be set to 0b11111
> > otherwise the instruction behaviour becomes CONSTRAINED UNPREDICTABLE.
> > 
> > Currenly, its usage is encoded as a system register write, with a constant
> > 0 value:
> > 
> > write_sysreg_s(0, GICV5_OP_GIC_CDEOI)
> > 
> > While compiling with GCC, the 0 constant value, through these asm
> > constraints and modifiers ('x' modifier and 'Z' constraint combo):
> > 
> > asm volatile(__msr_s(r, "%x0") : : "rZ" (__val));
> > 
> > forces the compiler to issue the XZR register for the MSR operation (ie
> > that corresponds to Rt == 0b11111) issuing the right instruction encoding.
> > 
> > Unfortunately LLVM does not yet understand that modifier/constraint
> > combo so it ends up issuing a different register from XZR for the MSR
> > source, which in turns means that it encodes the GIC CDEOI instruction
> > wrongly and the instruction behaviour becomes CONSTRAINED UNPREDICTABLE
> > that we must prevent.
> > 
> > Add a conditional to write_sysreg_s() macro that detects whether it
> > is passed a constant 0 value and issues an MSR write with XZR as source
> > register - explicitly doing what the asm modifier/constraint is meant to
> > achieve through constraints/modifiers, fixing the LLVM compilation issue.
> > 
> > Fixes: 7ec80fb3f025 ("irqchip/gic-v5: Add GICv5 PPI support")
> > Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
> > Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
> > Acked-by: Marc Zyngier <maz@kernel.org>
> > Cc: stable@vger.kernel.org
> > Cc: Sascha Bischoff <sascha.bischoff@arm.com>
> > Cc: Will Deacon <will@kernel.org>
> > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > Cc: Mark Rutland <mark.rutland@arm.com>
> > Cc: Marc Zyngier <maz@kernel.org>
> 
> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
> 
> (unless Will sends another pull request before -rc1, I'll pick this
> patch shortly after)

I'm not planning to send anything until the -rc3 timeframe now as I'm
going fishing for a couple of weeks :)

Will