[PATCH 0/2] dts: arm64: freescale: Update USB oc settings for PHYTEC i.MX8MM boards

[PATCH 0/2] dts: arm64: freescale: Update USB oc settings for PHYTEC i.MX8MM boards

[Teresa Remmet]

Update USB over-current settings for phyBOARD-Polis and phyGATE-Tauri-L.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
---
Teresa Remmet (2):
      arm64: dts: imx8mm-phyboard-polis-rdk: Add USB1 OC pin configuration
      arm64: dts: imx8mm-phygate-tauri-l: Update pad ctl for USB OC pin

 arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts | 8 ++++++++
 arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts    | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)
---
base-commit: e5f0a698b34ed76002dc5cff3804a61c80233a7a
change-id: 20250930-wip-t-remmet-phytec-de-upstream-85274fadf1e1

Best regards,
-- 
Teresa Remmet <t.remmet@phytec.de>

[PATCH 1/2] arm64: dts: imx8mm-phyboard-polis-rdk: Add USB1 OC pin configuration

[Teresa Remmet]

Add USB1 OC pin configuration for proper over-current detection.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
---
 arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
index be470cfb03d7..35d8c5ab3547 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
@@ -285,6 +285,8 @@ &usbotg1 {
 	over-current-active-low;
 	samsung,picophy-pre-emp-curr-control = <3>;
 	samsung,picophy-dc-vol-level-adjust = <7>;
+	pinctrl-0 = <&pinctrl_usbotg1>;
+	pinctrl-names = "default";
 	srp-disable;
 	vbus-supply = <&reg_usb_otg1_vbus>;
 	status = "okay";
@@ -458,6 +460,12 @@ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x00
 		>;
 	};
 
+	pinctrl_usbotg1: usbotg1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC	0x00
+		>;
+	};
+
 	pinctrl_usdhc1: usdhc1grp {
 		fsl,pins = <
 			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x182

-- 
2.25.1

[PATCH 2/2] arm64: dts: imx8mm-phygate-tauri-l: Update pad ctl for USB OC pin

[Teresa Remmet]

Disable Hysteresis Enable Field in pad ctl register for USB OC pin
as this is more appropriate for the signal form in our case.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
---
 arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts
index 755cf9cacd22..2ecc8b3c67da 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts
@@ -452,7 +452,7 @@ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x00
 
 	pinctrl_usbotg1: usbotg1grp {
 		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC	0x80
+			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC	0x00
 		>;
 	};
 

-- 
2.25.1

Re: [PATCH 0/2] dts: arm64: freescale: Update USB oc settings for PHYTEC i.MX8MM boards

[Peng Fan]

On Wed, Oct 01, 2025 at 02:43:26PM +0200, Teresa Remmet wrote:
>Update USB over-current settings for phyBOARD-Polis and phyGATE-Tauri-L.
>
>Signed-off-by: Teresa Remmet <t.remmet@phytec.de>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

Re: [PATCH 0/2] dts: arm64: freescale: Update USB oc settings for PHYTEC i.MX8MM boards

[Shawn Guo]

On Wed, Oct 01, 2025 at 02:43:26PM +0200, Teresa Remmet wrote:
> Teresa Remmet (2):
>       arm64: dts: imx8mm-phyboard-polis-rdk: Add USB1 OC pin configuration
>       arm64: dts: imx8mm-phygate-tauri-l: Update pad ctl for USB OC pin

Applied both, thanks!