[PATCH 08/15] arm64: dts: mediatek: mt7981b-openwrt-one: Enable PCIe and USB

Sjoerd Simons
2025-10-16T10:09:17Z

Enable the PCIe controller and USB3 XHCI host on the OpenWrt One
board. The USB controller is configured for USB 2.0 only mode, as the
shared USB3/PCIe PHY is dedicated to PCIe functionality on this board.

Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
---
.../boot/dts/mediatek/mt7981b-openwrt-one.dts | 43 ++++++++++++++++++++++
1 file changed, 43 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts
index f836059d7f475..b6ca628ee72fd 100644
--- a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts
@@ -20,9 +20,40 @@ memory@40000000 {
reg = <0 0x40000000 0 0x40000000>;
device_type = "memory";
};
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pins>;
+ status = "okay";
};

&pio {
+ pcie_pins: pcie-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_pereset";
+ };
+ };
+
uart0_pins: uart0-pins {
mux {
function = "uart";
@@ -36,3 +67,15 @@ &uart0 {
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
+
+&usb_phy {
+ status = "okay";
+};
+
+&xhci {
+ phys = <&u2port0 PHY_TYPE_USB2>;
+ vusb33-supply = <&reg_3p3v>;
+ vbus-supply = <&reg_5v>;
+ mediatek,u3p-dis-msk = <0x01>;
+ status = "okay";
+};

--
2.51.0