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From: Niklas Cassel <cassel@kernel.org>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"Shawn Lin" <shawn.lin@rock-chips.com>,
	"Kever Yang" <kever.yang@rock-chips.com>,
	"Simon Xue" <xxm@rock-chips.com>,
	"Damien Le Moal" <dlemoal@kernel.org>,
	"Dragan Simic" <dsimic@manjaro.org>,
	"FUKAUMI Naoki" <naoki@radxa.com>,
	"Diederik de Haas" <diederik@cknow-tech.com>,
	stable@vger.kernel.org,
	"Manivannan Sadhasivam" <manivannan.sadhasivam@oss.qualcomm.com>,
	linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org
Subject: Re: [PATCH v2] PCI: dw-rockchip: Disable L1 substates
Date: Fri, 17 Oct 2025 18:26:04 +0200	[thread overview]
Message-ID: <aPJuHCuA2QempRui@ryzen> (raw)
In-Reply-To: <20251016172504.GA991252@bhelgaas>

On Thu, Oct 16, 2025 at 12:25:04PM -0500, Bjorn Helgaas wrote:
> On Thu, Oct 16, 2025 at 11:04:22AM +0200, Niklas Cassel wrote:
> > The L1 substates support requires additional steps to work, see e.g.
> > section '11.6.6.4 L1 Substate' in the RK3588 TRM V1.0.
> > 
> > These steps are currently missing from the driver.
> 
> Can we outline here specifically what is missing?

Sure.

> 
> > While this has always been a problem when using e.g.
> > CONFIG_PCIEASPM_POWER_SUPERSAVE=y, the problem became more apparent after
> > commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for
> > devicetree platforms"), which enabled ASPM also for
> > CONFIG_PCIEASPM_DEFAULT=y.
> 
> Should also be able to trigger this problem regardless of
> CONFIG_PCIEASPM_* by using /sys/bus/pci/devices/.../link/l1_2_aspm.
> 
> > Disable L1 substates until proper support is added.
> 
> I would word this more like "prevent advertising L1 Substates support"
> since we're not actually *disabling* anything here.

Sure.

> 
> If the RK3588 TRM is publicly available, a URL here would be helpful.

I couldn't find it on any official rockchip or radxa URL.


Will submit a v3 that fixes your comments.


Kind regards,
Niklas


      parent reply	other threads:[~2025-10-17 16:26 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-16  9:04 [PATCH v2] PCI: dw-rockchip: Disable L1 substates Niklas Cassel
2025-10-16 10:00 ` Shawn Lin
2025-10-16 17:25 ` Bjorn Helgaas
2025-10-16 17:53   ` Bjorn Helgaas
2025-10-17 16:26   ` Niklas Cassel [this message]

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