[PATCH v3 0/7] iommu/arm-smmu-v3: Introduce an RCU-protected invalidation array

Nicolin Chen
2025-10-15T19:43:56Z

This is a work based on Jason's design and algorithm. This implementation
follows his initial draft and revising as well.

The new arm_smmu_invs array is an RCU-protected array, mutated when device
attach to the domain, iterated when an invalidation is required for IOPTE
changes in this domain. This keeps the current invalidation efficiency of
a smb_mb() followed by a conditional rwlock replacing the atomic/spinlock
combination.

A new data structure is defined for the array and its entry, representing
invalidation operations, such as S1_ASID, S2_VMID, and ATS. The algorithm
adds and deletes array entries efficiently and also keeps the array sorted
so as to group similar invalidations into batches.

During an invalidation, a new invalidation function iterates domain->invs,
and converts each entry to the corresponding invalidation command(s). This
new function is fully compatible with all the existing use cases, allowing
a simple rework/replacement.

Some races to keep in mind:

1) A domain can be shared across SMMU instances. When an SMMU instance is
removed, the updated invs array has to be sync-ed via synchronize_rcu()
to prevent an concurrent invalidation routine that is accessing the old
array from issuing commands to the removed SMMU instance.

2) When there are concurrent IOPTE changes (followed by invalidations) and
a domain attachment, the new attachment must not become out of sync at
the HW level, meaning that an STE store and invalidation array load must
be sequenced by the CPU's memory model.

3) When an ATS-enabled device attaches to a blocking domain, the core code
requires a hard fence to ensure all ATS invalidations to the device are
completed. Relying on RCU alone requires calling synchronize_rcu() that
can be too slow. Instead, when ATS is in use, hold a conditional rwlock
till all concurrent invalidations are finished.

Related future work and dependent projects:

* NVIDIA is building systems with > 10 SMMU instances where > 8 are being
used concurrently in a single VM. So having 8 copies of an identical S2
page table is not efficient. Instead, all vSMMU instances should check
compatibility on a shared S2 iopt, to eliminate 7 copies.

Previous attempt based on the list/spinlock design:
iommu/arm-smmu-v3: Allocate vmid per vsmmu instead of s2_parent
https://lore.kernel.org/all/cover.1744692494.git.nicolinc@nvidia.com/
now can adopt this invs array, avoiding adding complex lists/locks.

* The guest support for BTM requires temporarily invalidating two ASIDs
for a single instance. When it renumbers ASIDs this can now be done via
the invs array.

* SVA with multiple devices being used by a single process (NVIDIA today
has 4-8) sequentially iterates the invalidations through all instances.
This ignores the HW concurrency available in each instance. It would be
nice to not spin on each sync but go forward and issue batches to other
instances also. Reducing to a single SVA domain shared across instances
is required to look at this.

This is on Github:
https://github.com/nicolinc/iommufd/commits/arm_smmu_invs-v3

Changelog
v3:
* Add Reviewed/Acked-by from Jason and Balbir
* Rebase on v6.18-rc1
* Drop arm_smmu_invs_dbg()
* Improve kdocs and inline/commit comments
* Rename arm_smmu_invs_cmp to arm_smmu_inv_cmp
* Rename arm_smmu_invs_merge_cmp to arm_smmu_invs_cmp
* Call arm_smmu_invs_flush_iotlb_tags() from arm_smmu_invs_unref()
* Unconditionally trim the invs->num_invs inside arm_smmu_invs_unref(),
and simplify arm_smmu_install_old_domain_invs().
v2:
https://lore.kernel.org/all/cover.1757373449.git.nicolinc@nvidia.com/
* Rebase on v6.17-rc5
* Improve kdocs and inline comments
* Add arm_smmu_invs_dbg() for tracing
* Use users refcount to replace todel flag
* Initialize num_invs in arm_smmu_invs_alloc()
* Add a struct arm_smmu_inv_state to group invs pointers
* Add in struct arm_smmu_invs two flags (has_ats and old)
* Rename master->invs to master->build_invs, and sort the array
* Rework arm_smmu_domain_inv_range() and arm_smmu_invs_end_batch()
* Copy entries by struct arm_smmu_inv in arm_smmu_master_build_invs()
* Add arm_smmu_invs_flush_iotlb_tags() for IOTLB flush by last device
* Rework three invs mutation helpers, and prioritize use the in-place
mutation for detach
* Take writer's lock unconditionally but keep it short, and only take
reader's lock conditionally on a has_ats flag
v1:
https://lore.kernel.org/all/cover.1755131672.git.nicolinc@nvidia.com/

Thanks
Nicolin

Jason Gunthorpe (1):
iommu/arm-smmu-v3: Introduce a per-domain arm_smmu_invs array

Nicolin Chen (6):
iommu/arm-smmu-v3: Explicitly set smmu_domain->stage for SVA
iommu/arm-smmu-v3: Add an inline arm_smmu_domain_free()
iommu/arm-smmu-v3: Pre-allocate a per-master invalidation array
iommu/arm-smmu-v3: Populate smmu_domain->invs when attaching masters
iommu/arm-smmu-v3: Add arm_smmu_invs based arm_smmu_domain_inv_range()
iommu/arm-smmu-v3: Perform per-domain invalidations using
arm_smmu_invs

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 135 ++-
.../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 32 +-
.../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 93 ++
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 839 +++++++++++++++---
4 files changed, 924 insertions(+), 175 deletions(-)

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2.43.0