[PATCH 0/3] arm64: dts: PCI: lx2160 use fsl,lx2160ar2-pcie

[PATCH 0/3] arm64: dts: PCI: lx2160 use fsl,lx2160ar2-pcie

[Frank Li]

Only lx2160 rev1 use mobivel PCIe controller. Rev2 switch to use designware
PCIe controller. Rev2 is mass production version. Rev1 will not be
maintained and used in future. And no road map to use mobivel PCIe
controller.

Driver part:
https://lore.kernel.org/imx/20240808-mobivel_cleanup-v1-0-f4f6ea5b16de@nxp.com/
Bjorn and mani have some concern about delete it directly.

V2 try not to build defaultly to make change visuable to do prepare for
futher clean up.
https://lore.kernel.org/imx/20240815182420.58821-1-Frank.Li@nxp.com/

Dts part.
previous version:
https://lore.kernel.org/imx/ac41ac85-fdf5-4aa8-953d-6b3ab3c23f37@kernel.org/

2020 yang li try to do the same thing.
https://lore.kernel.org/all/20220817202538.21493-2-leoyang.li@nxp.com/

Olof Johansson report (HoneyComb LX2K) use ver1 chip. NXP can't prevent
3rd parting to build their production with evaluation chip. Rev1's
informaiton have been removed from nxp.com.

Any way, to reduce impact, just apply rev2 to nxp's boards, qds and rdb.
It can apply to more boards gradually.

To: Bjorn Helgaas <bhelgaas@google.com>
To: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Krzysztof Wilczyński <kw@linux.com>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Shawn Guo <shawnguo@kernel.org>
To: Olof Johansson <olof@lixom.net>
Cc: Krzysztof Wilczyński <kwilczynski@kernel.org>
Cc: linux-pci@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: imx@lists.linux.dev

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Frank Li (3):
      dt-bindings: PCI: layerscape-pci: Replace fsl,lx2160a-pcie with fsl,lx2160ar2-pcie
      arm64: dts: fsl-lx2160a: add rev2 support
      arm64: dts: fsl-lx2160a: include rev2 chip's dts

 .../bindings/pci/fsl,layerscape-pcie.yaml          |  26 ++--
 arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts  |   2 +-
 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts  |   2 +-
 .../arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi | 170 +++++++++++++++++++++
 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi     |   2 +-
 arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts  |   2 +-
 6 files changed, 188 insertions(+), 16 deletions(-)
---
base-commit: 182a1659076d1ae4115534f43e40e94001fd68a6
change-id: 20240816-2160r2-4783f2f067e8

Best regards,
---
Frank Li <Frank.Li@nxp.com>

[PATCH 1/3] dt-bindings: PCI: layerscape-pci: Replace fsl,lx2160a-pcie with fsl,lx2160ar2-pcie

[Frank Li]

fsl,lx2160a-pcie compatible is used for mobivel according to
Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt

fsl,layerscape-pcie.yaml is used for designware PCIe controller binding. So
change it to fsl,lx2160ar2-pcie and allow fall back to fsl,ls2088a-pcie.

Sort compatible string.

Fixes: 24cd7ecb3886 ("dt-bindings: PCI: layerscape-pci: Convert to YAML format")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 .../bindings/pci/fsl,layerscape-pcie.yaml          | 26 ++++++++++++----------
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
index 793986c5af7ff..daeab5c0758d1 100644
--- a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
@@ -22,18 +22,20 @@ description:
 
 properties:
   compatible:
-    enum:
-      - fsl,ls1021a-pcie
-      - fsl,ls2080a-pcie
-      - fsl,ls2085a-pcie
-      - fsl,ls2088a-pcie
-      - fsl,ls1088a-pcie
-      - fsl,ls1046a-pcie
-      - fsl,ls1043a-pcie
-      - fsl,ls1012a-pcie
-      - fsl,ls1028a-pcie
-      - fsl,lx2160a-pcie
-
+    oneOf:
+      - enum:
+          - fsl,ls1012a-pcie
+          - fsl,ls1021a-pcie
+          - fsl,ls1028a-pcie
+          - fsl,ls1043a-pcie
+          - fsl,ls1046a-pcie
+          - fsl,ls1088a-pcie
+          - fsl,ls2080a-pcie
+          - fsl,ls2085a-pcie
+          - fsl,ls2088a-pcie
+      - items:
+          - const: fsl,lx2160ar2-pcie
+          - const: fsl,ls2088a-pcie
   reg:
     maxItems: 2
 

-- 
2.34.1

[PATCH 2/3] arm64: dts: fsl-lx2160a: add rev2 support

[Frank Li]

Add rev2 dtsi. Although uboot fixup can change compatible string
fsl,lx2160a-pcie to fsl,ls2088a-pcie since 2019, it is quite confused and
should correctly reflect hardware status. So add fsl-lx2160a-rev2.dtsi to
overwrite pcie's compatible string.

Add PCIe EP nodes.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 .../arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi | 170 +++++++++++++++++++++
 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi     |   2 +-
 2 files changed, 171 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi
new file mode 100644
index 0000000000000..432e54f6f7ae5
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree file for LX2160 REV2
+//
+// Copyright 2025 NXP
+
+/dts-v1/;
+
+#include "fsl-lx2160a.dtsi"
+
+&pcie1 {
+	compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+	reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
+	      0x80 0x00000000 0x0 0x00002000>; /* configuration space */
+	reg-names = "regs", "config";
+
+	ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000
+		  0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
+
+	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "intr";
+
+	/delete-property/ apio-wins;
+	/delete-property/ ppio-wins;
+};
+
+&pcie2 {
+	compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+	reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
+	       0x88 0x00000000 0x0 0x00002000>; /* configuration space */
+	reg-names = "regs", "config";
+
+	ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000
+		  0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>;
+
+	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "intr";
+
+	/delete-property/ apio-wins;
+	/delete-property/ ppio-wins;
+};
+
+&pcie3 {
+	compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+	reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
+	       0x90 0x00000000 0x0 0x00002000>; /* configuration space */
+	reg-names = "regs", "config";
+
+	ranges = <0x81000000 0x0 0x00000000 0x90 0x00010000 0x0 0x00010000
+		  0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>;
+
+	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "intr";
+
+	/delete-property/ apio-wins;
+	/delete-property/ ppio-wins;
+};
+
+
+&pcie4 {
+	compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+	reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
+	       0x98 0x00000000 0x0 0x00002000>; /* configuration space */
+	reg-names = "regs", "config";
+
+	ranges = <0x81000000 0x0 0x00000000 0x98 0x00010000 0x0 0x00010000
+		  0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>;
+
+	interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "intr";
+
+	/delete-property/ apio-wins;
+	/delete-property/ ppio-wins;
+};
+
+&pcie5 {
+	compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+	reg = <0x00 0x03800000 0x0 0x00100000   /* controller registers */
+	       0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
+	reg-names = "regs", "config";
+
+	ranges = <0x81000000 0x0 0x00000000 0xa0 0x00010000 0x0 0x00010000
+		  0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>;
+
+	interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "intr";
+
+	/delete-property/ apio-wins;
+	/delete-property/ ppio-wins;
+};
+
+&pcie6 {
+	compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
+	reg = <0x00 0x03900000 0x0 0x00100000   /* controller registers */
+	       0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
+	reg-names = "regs", "config";
+
+	ranges = <0x81000000 0x0 0x00000000 0xa8 0x00010000 0x0 0x00010000
+		  0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;
+
+	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+	interrupt-names = "intr";
+
+	/delete-property/ apio-wins;
+	/delete-property/ ppio-wins;
+};
+
+&soc {
+	pcie_ep1: pcie-ep@3400000 {
+		compatible = "fsl,lx2160ar2-pcie-ep";
+		reg = <0x00 0x03400000 0x0 0x00100000
+		       0x80 0x00000000 0x8 0x00000000>;
+		reg-names = "regs", "addr_space";
+		num-ob-windows = <8>;
+		num-ib-windows = <8>;
+		status = "disabled";
+	};
+
+	pcie_ep2: pcie-ep@3500000 {
+		compatible = "fsl,lx2160ar2-pcie-ep";
+		reg = <0x00 0x03500000 0x0 0x00100000
+		       0x88 0x00000000 0x8 0x00000000>;
+		reg-names = "regs", "addr_space";
+		num-ob-windows = <8>;
+		num-ib-windows = <8>;
+		status = "disabled";
+	};
+
+	pcie_ep3: pcie-ep@3600000 {
+		compatible = "fsl,lx2160ar2-pcie-ep";
+		reg = <0x00 0x03600000 0x0 0x00100000
+		       0x90 0x00000000 0x8 0x00000000>;
+		reg-names = "regs", "addr_space";
+		num-ob-windows = <256>;
+		num-ib-windows = <24>;
+		status = "disabled";
+	};
+
+	pcie_ep4: pcie-ep@3700000 {
+		compatible = "fsl,lx2160ar2-pcie-ep";
+		reg = <0x00 0x03700000 0x0 0x00100000
+		       0x98 0x00000000 0x8 0x00000000>;
+		reg-names = "regs", "addr_space";
+		num-ob-windows = <8>;
+		num-ib-windows = <8>;
+		status = "disabled";
+	};
+
+
+	pcie_ep5: pcie-ep@3800000 {
+		compatible = "fsl,lx2160ar2-pcie-ep";
+		reg = <0x00 0x03800000 0x0 0x00100000
+		       0xa0 0x00000000 0x8 0x00000000>;
+		reg-names = "regs", "addr_space";
+		num-ob-windows = <256>;
+		num-ib-windows = <24>;
+		status = "disabled";
+	};
+
+	pcie_ep6: pcie-ep@3900000 {
+		compatible = "fsl,lx2160ar2-pcie-ep";
+		reg = <0x00 0x03900000 0x0 0x00100000
+		       0xa8 0x00000000 0x8 0x00000000>;
+		reg-names = "regs", "addr_space";
+		num-ob-windows = <8>;
+		num-ib-windows = <8>;
+		status = "disabled";
+	};
+};
+
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 26c7ca31e22e7..b2dea03e1b8ec 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -613,7 +613,7 @@ cluster2-3-crit {
 		};
 	};
 
-	soc {
+	soc: soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;
 		#size-cells = <2>;

-- 
2.34.1

[PATCH 3/3] arm64: dts: fsl-lx2160a: include rev2 chip's dts

[Frank Li]

The mass production lx2160 rev2 use designware PCIe Controller. Old Rev1
which use mobivel PCIe controller was not supported. Although uboot
fixup can change compatible string fsl,lx2160a-pcie to fsl,ls2088a-pcie
since 2019, it is quite confused and should correctly reflect hardware
status in dtb. Change freescale's board to use rev2's dtsi firstly.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 2 +-
 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 2 +-
 arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
index 4d721197d837e..71d0d6745e44a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
@@ -6,7 +6,7 @@
 
 /dts-v1/;
 
-#include "fsl-lx2160a.dtsi"
+#include "fsl-lx2160a-rev2.dtsi"
 
 / {
 	model = "NXP Layerscape LX2160AQDS";
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 0c44b3cbef773..2373e1c371e8c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -6,7 +6,7 @@
 
 /dts-v1/;
 
-#include "fsl-lx2160a.dtsi"
+#include "fsl-lx2160a-rev2.dtsi"
 
 / {
 	model = "NXP Layerscape LX2160ARDB";
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
index 9f5ff1ffe7d5e..7a595fddc0273 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
@@ -6,7 +6,7 @@
 
 /dts-v1/;
 
-#include "fsl-lx2160a.dtsi"
+#include "fsl-lx2160a-rev2.dtsi"
 
 / {
 	model = "NXP Layerscape LX2162AQDS";

-- 
2.34.1

Re: [PATCH 1/3] dt-bindings: PCI: layerscape-pci: Replace fsl,lx2160a-pcie with fsl,lx2160ar2-pcie

[Rob Herring (Arm)]

On Mon, 26 Aug 2024 17:38:32 -0400, Frank Li wrote:
> fsl,lx2160a-pcie compatible is used for mobivel according to
> Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
> 
> fsl,layerscape-pcie.yaml is used for designware PCIe controller binding. So
> change it to fsl,lx2160ar2-pcie and allow fall back to fsl,ls2088a-pcie.
> 
> Sort compatible string.
> 
> Fixes: 24cd7ecb3886 ("dt-bindings: PCI: layerscape-pci: Convert to YAML format")
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>  .../bindings/pci/fsl,layerscape-pcie.yaml          | 26 ++++++++++++----------
>  1 file changed, 14 insertions(+), 12 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 1/3] dt-bindings: PCI: layerscape-pci: Replace fsl,lx2160a-pcie with fsl,lx2160ar2-pcie

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 2033 bytes --]

On Mon, Aug 26, 2024 at 05:38:32PM -0400, Frank Li wrote:
> fsl,lx2160a-pcie compatible is used for mobivel according to
> Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
> 
> fsl,layerscape-pcie.yaml is used for designware PCIe controller binding. So
> change it to fsl,lx2160ar2-pcie and allow fall back to fsl,ls2088a-pcie.
> 
> Sort compatible string.
> 
> Fixes: 24cd7ecb3886 ("dt-bindings: PCI: layerscape-pci: Convert to YAML format")

I don't understand what this fixes tag is for, this is a brand new
compatible that you are adding, why does it need a fixes tag pointing to
the conversion?

> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>  .../bindings/pci/fsl,layerscape-pcie.yaml          | 26 ++++++++++++----------
>  1 file changed, 14 insertions(+), 12 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
> index 793986c5af7ff..daeab5c0758d1 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
> @@ -22,18 +22,20 @@ description:
>  
>  properties:
>    compatible:
> -    enum:
> -      - fsl,ls1021a-pcie
> -      - fsl,ls2080a-pcie
> -      - fsl,ls2085a-pcie
> -      - fsl,ls2088a-pcie
> -      - fsl,ls1088a-pcie
> -      - fsl,ls1046a-pcie
> -      - fsl,ls1043a-pcie
> -      - fsl,ls1012a-pcie
> -      - fsl,ls1028a-pcie
> -      - fsl,lx2160a-pcie
> -
> +    oneOf:
> +      - enum:
> +          - fsl,ls1012a-pcie
> +          - fsl,ls1021a-pcie
> +          - fsl,ls1028a-pcie
> +          - fsl,ls1043a-pcie
> +          - fsl,ls1046a-pcie
> +          - fsl,ls1088a-pcie
> +          - fsl,ls2080a-pcie
> +          - fsl,ls2085a-pcie
> +          - fsl,ls2088a-pcie
> +      - items:
> +          - const: fsl,lx2160ar2-pcie
> +          - const: fsl,ls2088a-pcie
>    reg:
>      maxItems: 2
>  
> 
> -- 
> 2.34.1
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 1/3] dt-bindings: PCI: layerscape-pci: Replace fsl,lx2160a-pcie with fsl,lx2160ar2-pcie

[Frank Li]

On Tue, Aug 27, 2024 at 05:14:32PM +0100, Conor Dooley wrote:
> On Mon, Aug 26, 2024 at 05:38:32PM -0400, Frank Li wrote:
> > fsl,lx2160a-pcie compatible is used for mobivel according to
> > Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
> >
> > fsl,layerscape-pcie.yaml is used for designware PCIe controller binding. So
> > change it to fsl,lx2160ar2-pcie and allow fall back to fsl,ls2088a-pcie.
> >
> > Sort compatible string.
> >
> > Fixes: 24cd7ecb3886 ("dt-bindings: PCI: layerscape-pci: Convert to YAML format")
>
> I don't understand what this fixes tag is for, this is a brand new
> compatible that you are adding, why does it need a fixes tag pointing to
> the conversion?

Because previous convert wrongly included "fsl,lx2160a-pcie" here, which
already used for mobivel pci controler, descripted in
layerscape-pcie-gen4.txt.

This patch fix this problem, rename fsl,lx2160a-pcie to fsl,lx2160ar2-pcie

>
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> >  .../bindings/pci/fsl,layerscape-pcie.yaml          | 26 ++++++++++++----------
> >  1 file changed, 14 insertions(+), 12 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
> > index 793986c5af7ff..daeab5c0758d1 100644
> > --- a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
> > @@ -22,18 +22,20 @@ description:
> >
> >  properties:
> >    compatible:
> > -    enum:
> > -      - fsl,ls1021a-pcie
> > -      - fsl,ls2080a-pcie
> > -      - fsl,ls2085a-pcie
> > -      - fsl,ls2088a-pcie
> > -      - fsl,ls1088a-pcie
> > -      - fsl,ls1046a-pcie
> > -      - fsl,ls1043a-pcie
> > -      - fsl,ls1012a-pcie
> > -      - fsl,ls1028a-pcie
> > -      - fsl,lx2160a-pcie
> > -
> > +    oneOf:
> > +      - enum:
> > +          - fsl,ls1012a-pcie
> > +          - fsl,ls1021a-pcie
> > +          - fsl,ls1028a-pcie
> > +          - fsl,ls1043a-pcie
> > +          - fsl,ls1046a-pcie
> > +          - fsl,ls1088a-pcie
> > +          - fsl,ls2080a-pcie
> > +          - fsl,ls2085a-pcie
> > +          - fsl,ls2088a-pcie
> > +      - items:
> > +          - const: fsl,lx2160ar2-pcie
> > +          - const: fsl,ls2088a-pcie
> >    reg:
> >      maxItems: 2
> >
> >
> > --
> > 2.34.1
> >

Re: [PATCH 1/3] dt-bindings: PCI: layerscape-pci: Replace fsl,lx2160a-pcie with fsl,lx2160ar2-pcie

[Conor Dooley]

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On Tue, Aug 27, 2024 at 12:32:42PM -0400, Frank Li wrote:
> On Tue, Aug 27, 2024 at 05:14:32PM +0100, Conor Dooley wrote:
> > On Mon, Aug 26, 2024 at 05:38:32PM -0400, Frank Li wrote:
> > > fsl,lx2160a-pcie compatible is used for mobivel according to
> > > Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
> > >
> > > fsl,layerscape-pcie.yaml is used for designware PCIe controller binding. So
> > > change it to fsl,lx2160ar2-pcie and allow fall back to fsl,ls2088a-pcie.
> > >
> > > Sort compatible string.
> > >
> > > Fixes: 24cd7ecb3886 ("dt-bindings: PCI: layerscape-pci: Convert to YAML format")
> >
> > I don't understand what this fixes tag is for, this is a brand new
> > compatible that you are adding, why does it need a fixes tag pointing to
> > the conversion?
> 
> Because previous convert wrongly included "fsl,lx2160a-pcie" here, which
> already used for mobivel pci controler, descripted in
> layerscape-pcie-gen4.txt.
> 
> This patch fix this problem, rename fsl,lx2160a-pcie to fsl,lx2160ar2-pcie

Ah, I see that now. Lost in the noise of reordering the list first time
around.

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Re: [PATCH 1/3] dt-bindings: PCI: layerscape-pci: Replace fsl,lx2160a-pcie with fsl,lx2160ar2-pcie

[Krzysztof Wilczyński]

Hello,

> fsl,lx2160a-pcie compatible is used for mobivel according to
> Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
> 
> fsl,layerscape-pcie.yaml is used for designware PCIe controller binding. So
> change it to fsl,lx2160ar2-pcie and allow fall back to fsl,ls2088a-pcie.
> 
> Sort compatible string.

Applied to dt-bindings, thank you!

[1/1] dt-bindings: PCI: layerscape-pci: Replace fsl,lx2160a-pcie with fsl,lx2160ar2-pcie
      https://git.kernel.org/pci/pci/c/1a1bf58897d2

	Krzysztof

Re: [PATCH 2/3] arm64: dts: fsl-lx2160a: add rev2 support

[Frank Li]

On Mon, Aug 26, 2024 at 05:38:33PM -0400, Frank Li wrote:
> Add rev2 dtsi. Although uboot fixup can change compatible string
> fsl,lx2160a-pcie to fsl,ls2088a-pcie since 2019, it is quite confused and
> should correctly reflect hardware status. So add fsl-lx2160a-rev2.dtsi to
> overwrite pcie's compatible string.
>
> Add PCIe EP nodes.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---

Shawn:

	Do you have chance to check this?

best regards
Frank

>  .../arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi | 170 +++++++++++++++++++++
>  arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi     |   2 +-
>  2 files changed, 171 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi
> new file mode 100644
> index 0000000000000..432e54f6f7ae5
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi
> @@ -0,0 +1,170 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +//
> +// Device Tree file for LX2160 REV2
> +//
> +// Copyright 2025 NXP
> +
> +/dts-v1/;
> +
> +#include "fsl-lx2160a.dtsi"
> +
> +&pcie1 {
> +	compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
> +	reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
> +	      0x80 0x00000000 0x0 0x00002000>; /* configuration space */
> +	reg-names = "regs", "config";
> +
> +	ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000
> +		  0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
> +
> +	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> +	interrupt-names = "intr";
> +
> +	/delete-property/ apio-wins;
> +	/delete-property/ ppio-wins;
> +};
> +
> +&pcie2 {
> +	compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
> +	reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
> +	       0x88 0x00000000 0x0 0x00002000>; /* configuration space */
> +	reg-names = "regs", "config";
> +
> +	ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000
> +		  0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>;
> +
> +	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> +	interrupt-names = "intr";
> +
> +	/delete-property/ apio-wins;
> +	/delete-property/ ppio-wins;
> +};
> +
> +&pcie3 {
> +	compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
> +	reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
> +	       0x90 0x00000000 0x0 0x00002000>; /* configuration space */
> +	reg-names = "regs", "config";
> +
> +	ranges = <0x81000000 0x0 0x00000000 0x90 0x00010000 0x0 0x00010000
> +		  0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>;
> +
> +	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
> +	interrupt-names = "intr";
> +
> +	/delete-property/ apio-wins;
> +	/delete-property/ ppio-wins;
> +};
> +
> +
> +&pcie4 {
> +	compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
> +	reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
> +	       0x98 0x00000000 0x0 0x00002000>; /* configuration space */
> +	reg-names = "regs", "config";
> +
> +	ranges = <0x81000000 0x0 0x00000000 0x98 0x00010000 0x0 0x00010000
> +		  0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>;
> +
> +	interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
> +	interrupt-names = "intr";
> +
> +	/delete-property/ apio-wins;
> +	/delete-property/ ppio-wins;
> +};
> +
> +&pcie5 {
> +	compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
> +	reg = <0x00 0x03800000 0x0 0x00100000   /* controller registers */
> +	       0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
> +	reg-names = "regs", "config";
> +
> +	ranges = <0x81000000 0x0 0x00000000 0xa0 0x00010000 0x0 0x00010000
> +		  0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>;
> +
> +	interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
> +	interrupt-names = "intr";
> +
> +	/delete-property/ apio-wins;
> +	/delete-property/ ppio-wins;
> +};
> +
> +&pcie6 {
> +	compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
> +	reg = <0x00 0x03900000 0x0 0x00100000   /* controller registers */
> +	       0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
> +	reg-names = "regs", "config";
> +
> +	ranges = <0x81000000 0x0 0x00000000 0xa8 0x00010000 0x0 0x00010000
> +		  0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;
> +
> +	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> +	interrupt-names = "intr";
> +
> +	/delete-property/ apio-wins;
> +	/delete-property/ ppio-wins;
> +};
> +
> +&soc {
> +	pcie_ep1: pcie-ep@3400000 {
> +		compatible = "fsl,lx2160ar2-pcie-ep";
> +		reg = <0x00 0x03400000 0x0 0x00100000
> +		       0x80 0x00000000 0x8 0x00000000>;
> +		reg-names = "regs", "addr_space";
> +		num-ob-windows = <8>;
> +		num-ib-windows = <8>;
> +		status = "disabled";
> +	};
> +
> +	pcie_ep2: pcie-ep@3500000 {
> +		compatible = "fsl,lx2160ar2-pcie-ep";
> +		reg = <0x00 0x03500000 0x0 0x00100000
> +		       0x88 0x00000000 0x8 0x00000000>;
> +		reg-names = "regs", "addr_space";
> +		num-ob-windows = <8>;
> +		num-ib-windows = <8>;
> +		status = "disabled";
> +	};
> +
> +	pcie_ep3: pcie-ep@3600000 {
> +		compatible = "fsl,lx2160ar2-pcie-ep";
> +		reg = <0x00 0x03600000 0x0 0x00100000
> +		       0x90 0x00000000 0x8 0x00000000>;
> +		reg-names = "regs", "addr_space";
> +		num-ob-windows = <256>;
> +		num-ib-windows = <24>;
> +		status = "disabled";
> +	};
> +
> +	pcie_ep4: pcie-ep@3700000 {
> +		compatible = "fsl,lx2160ar2-pcie-ep";
> +		reg = <0x00 0x03700000 0x0 0x00100000
> +		       0x98 0x00000000 0x8 0x00000000>;
> +		reg-names = "regs", "addr_space";
> +		num-ob-windows = <8>;
> +		num-ib-windows = <8>;
> +		status = "disabled";
> +	};
> +
> +
> +	pcie_ep5: pcie-ep@3800000 {
> +		compatible = "fsl,lx2160ar2-pcie-ep";
> +		reg = <0x00 0x03800000 0x0 0x00100000
> +		       0xa0 0x00000000 0x8 0x00000000>;
> +		reg-names = "regs", "addr_space";
> +		num-ob-windows = <256>;
> +		num-ib-windows = <24>;
> +		status = "disabled";
> +	};
> +
> +	pcie_ep6: pcie-ep@3900000 {
> +		compatible = "fsl,lx2160ar2-pcie-ep";
> +		reg = <0x00 0x03900000 0x0 0x00100000
> +		       0xa8 0x00000000 0x8 0x00000000>;
> +		reg-names = "regs", "addr_space";
> +		num-ob-windows = <8>;
> +		num-ib-windows = <8>;
> +		status = "disabled";
> +	};
> +};
> +
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> index 26c7ca31e22e7..b2dea03e1b8ec 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> @@ -613,7 +613,7 @@ cluster2-3-crit {
>  		};
>  	};
>
> -	soc {
> +	soc: soc {
>  		compatible = "simple-bus";
>  		#address-cells = <2>;
>  		#size-cells = <2>;
>
> --
> 2.34.1
>

Re: [PATCH 2/3] arm64: dts: fsl-lx2160a: add rev2 support

[Shawn Guo]

On Mon, Aug 26, 2024 at 05:38:33PM -0400, Frank Li wrote:
> Add rev2 dtsi. Although uboot fixup can change compatible string
> fsl,lx2160a-pcie to fsl,ls2088a-pcie since 2019, it is quite confused and
> should correctly reflect hardware status. So add fsl-lx2160a-rev2.dtsi to
> overwrite pcie's compatible string.
> 
> Add PCIe EP nodes.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>

Applied, thanks!

Re: [PATCH 3/3] arm64: dts: fsl-lx2160a: include rev2 chip's dts

[Vladimir Oltean]

Hi Shawn,

On Mon, Aug 26, 2024 at 05:38:34PM -0400, Frank Li wrote:
> The mass production lx2160 rev2 use designware PCIe Controller. Old Rev1
> which use mobivel PCIe controller was not supported. Although uboot
> fixup can change compatible string fsl,lx2160a-pcie to fsl,ls2088a-pcie
> since 2019, it is quite confused and should correctly reflect hardware
> status in dtb. Change freescale's board to use rev2's dtsi firstly.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 2 +-
>  arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 2 +-
>  arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
> index 4d721197d837e..71d0d6745e44a 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
> @@ -6,7 +6,7 @@
>  
>  /dts-v1/;
>  
> -#include "fsl-lx2160a.dtsi"
> +#include "fsl-lx2160a-rev2.dtsi"
>  
>  / {
>  	model = "NXP Layerscape LX2160AQDS";
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> index 0c44b3cbef773..2373e1c371e8c 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> @@ -6,7 +6,7 @@
>  
>  /dts-v1/;
>  
> -#include "fsl-lx2160a.dtsi"
> +#include "fsl-lx2160a-rev2.dtsi"
>  
>  / {
>  	model = "NXP Layerscape LX2160ARDB";
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
> index 9f5ff1ffe7d5e..7a595fddc0273 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
> @@ -6,7 +6,7 @@
>  
>  /dts-v1/;
>  
> -#include "fsl-lx2160a.dtsi"
> +#include "fsl-lx2160a-rev2.dtsi"
>  
>  / {
>  	model = "NXP Layerscape LX2162AQDS";
> 
> -- 
> 2.34.1
> 
> 

Sorry for digging up an old thread, but I'm curious why you applied
patch 2/3 but not this one? Currently,
arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi has no user.

Thread here.
https://lore.kernel.org/lkml/20240826-2160r2-v1-0-106340d538d6@nxp.com/

Re: [PATCH 3/3] arm64: dts: fsl-lx2160a: include rev2 chip's dts

[Shawn Guo]

On Tue, Sep 23, 2025 at 02:10:38PM +0300, Vladimir Oltean wrote:
> Sorry for digging up an old thread, but I'm curious why you applied
> patch 2/3 but not this one? Currently,
> arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi has no user.

I'm not sure how I missed it :)  Thanks for asking.  Applied now.

Shawn