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From: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
To: "Russell King (Oracle)" <linux@armlinux.org.uk>
Cc: "Vladimir Oltean" <olteanv@gmail.com>,
	"Andrew Lunn" <andrew@lunn.ch>,
	"Heiner Kallweit" <hkallweit1@gmail.com>,
	"Alexandre Torgue" <alexandre.torgue@foss.st.com>,
	"Alexis Lothoré" <alexis.lothore@bootlin.com>,
	"Andrew Lunn" <andrew+netdev@lunn.ch>,
	"Boon Khai Ng" <boon.khai.ng@altera.com>,
	"Daniel Machon" <daniel.machon@microchip.com>,
	"David S. Miller" <davem@davemloft.net>,
	"Eric Dumazet" <edumazet@google.com>,
	"Furong Xu" <0x1207@gmail.com>,
	"Jacob Keller" <jacob.e.keller@intel.com>,
	"Jakub Kicinski" <kuba@kernel.org>,
	"Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-stm32@st-md-mailman.stormreply.com,
	"Maxime Chevallier" <maxime.chevallier@bootlin.com>,
	"Maxime Coquelin" <mcoquelin.stm32@gmail.com>,
	netdev@vger.kernel.org, "Paolo Abeni" <pabeni@redhat.com>,
	"Simon Horman" <horms@kernel.org>,
	"Yu-Chun Lin" <eleanor15x@gmail.com>
Subject: Re: [PATCH net-next 0/3] net: stmmac: phylink PCS conversion part 3 (dodgy stuff)
Date: Mon, 3 Nov 2025 17:47:35 +0530	[thread overview]
Message-ID: <aQidX6SPDbOQ5WKU@oss.qualcomm.com> (raw)
In-Reply-To: <aQiVWydDsRaMz8ua@shell.armlinux.org.uk>

On Mon, Nov 03, 2025 at 11:43:23AM +0000, Russell King (Oracle) wrote:
> On Mon, Nov 03, 2025 at 04:50:03PM +0530, Mohd Ayaan Anwar wrote:
> > On Mon, Nov 03, 2025 at 12:48:20PM +0200, Vladimir Oltean wrote:
> > > 
> > > As Russell partially pointed out, there are several assumptions in the
> > > Aquantia PHY driver and in phylink, three of them being that:
> > > - rate matching is only supported for PHY_INTERFACE_MODE_10GBASER and
> > >   PHY_INTERFACE_MODE_2500BASEX (thus not PHY_INTERFACE_MODE_SGMII)
> > > - if phy_get_rate_matching() returns RATE_MATCH_NONE for an interface,
> > >   pl->phy_state.rate_matching will also be RATE_MATCH_NONE when using
> > >   that interface
> > > - if rate matching is used, the PHY is configured to use it for all
> > >   media speeds <= phylink_interface_max_speed(link_state.interface)
> > > 
> > > Those assumptions are not validated very well against the ground truth
> > > from the PHY provisioning, so the next step would be for us to see that
> > > directly.
> > > 
> > > Please turn this print from aqr_gen2_read_global_syscfg() into something
> > > visible in dmesg, i.e. by replacing phydev_dbg() with phydev_info():
> > > 
> > > 		phydev_dbg(phydev,
> > > 			   "Media speed %d uses host interface %s with %s\n",
> > > 			   syscfg->speed, phy_modes(syscfg->interface),
> > > 			   syscfg->rate_adapt == AQR_RATE_ADAPT_NONE ? "no rate adaptation" :
> > > 			   syscfg->rate_adapt == AQR_RATE_ADAPT_PAUSE ? "rate adaptation through flow control" :
> > > 			   syscfg->rate_adapt == AQR_RATE_ADAPT_USX ? "rate adaptation through symbol replication" :
> > > 			   "unrecognized rate adaptation type");
> > 
> > Thanks. Looks like rate adaptation is only provisioned for 10M, which
> > matches my observation where phylink passes the exact speeds for
> > 100/1000/2500 but 1000 for 10M.
> 
> Hmm, I wonder what the PHY is doing for that then. stmmac will be
> programmed to read the Cisco SGMII in-band control word, and use
> that to determine whether symbol replication for slower speeds is
> being used.
> 
> If AQR115C is indicating 10M in the in-band control word, but is
> actually operating the link at 1G speed, things are not going to
> work, and I would say the PHY is broken to be doing that. The point
> of the SGMII in-band control word is to tell the MAC about the
> required symbol replication on the link for transmitting the slower
> data rates over the link.
> 
> stmmac unfortunately doesn't give access to the raw Cisco SGMII
> in-band control word. However, reading register 0xf8 bits 31:16 for
> dwmac4, or register 0xd8 bits 15:0 for dwmac1000 will give this
> information. In that bitfield, bits 2:1 give the speed. 2 = 1G,
> 1 = 100M, 0 = 10M.
> 

This is dwmac4 and I got the following values with devmem at different
link speeds:
1. 10M:		0x00080000  => Bit 2:1 = 0
2. 100M:	0x000A0000  => Bit 2:1 = 1
3. 1G: 		0x000D0000  => Bit 2:1 = 2

> -- 
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!


  parent reply	other threads:[~2025-11-03 12:17 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-25 20:47 [PATCH net-next 0/3] net: stmmac: phylink PCS conversion part 3 (dodgy stuff) Russell King (Oracle)
2025-10-25 20:48 ` [PATCH net-next 1/3] net: stmmac: configure AN control according to phylink Russell King (Oracle)
2025-10-25 20:48 ` [PATCH net-next 2/3] net: stmmac: report PCS configuration changes Russell King (Oracle)
2025-10-25 20:48 ` [PATCH net-next 3/3] net: stmmac: add support specifying PCS supported interfaces Russell King (Oracle)
2025-10-28 10:16   ` Maxime Chevallier
2025-10-28 10:35     ` Russell King (Oracle)
2025-10-28 10:40       ` Russell King (Oracle)
2025-10-28 11:26       ` Maxime Chevallier
2025-10-28 21:12 ` [PATCH net-next 0/3] net: stmmac: phylink PCS conversion part 3 (dodgy stuff) Mohd Ayaan Anwar
2025-10-29  9:22   ` Russell King (Oracle)
2025-10-30 13:20     ` Mohd Ayaan Anwar
2025-10-30 15:19       ` Russell King (Oracle)
2025-10-30 15:22         ` Russell King (Oracle)
2025-11-03  8:58           ` Mohd Ayaan Anwar
2025-11-03  9:52             ` Russell King (Oracle)
2025-11-03 10:18               ` Mohd Ayaan Anwar
2025-11-03 10:47                 ` Russell King (Oracle)
2025-11-03 10:48                 ` Vladimir Oltean
2025-11-03 11:20                   ` Mohd Ayaan Anwar
2025-11-03 11:43                     ` Russell King (Oracle)
2025-11-03 12:13                       ` Vladimir Oltean
2025-11-03 14:47                         ` Mohd Ayaan Anwar
2025-11-03 17:15                           ` Russell King (Oracle)
2025-11-03 17:02                         ` Russell King (Oracle)
2025-11-03 12:17                       ` Mohd Ayaan Anwar [this message]
2025-11-03 17:13                         ` Russell King (Oracle)
2025-11-05 15:46         ` Mohd Ayaan Anwar
2025-11-05 18:12           ` Russell King (Oracle)

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