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Mon, 03 Nov 2025 12:55:49 -0800 (PST) Received: from geday ([2804:7f2:800b:e79::dead:c001]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7acd623e091sm315775b3a.54.2025.11.03.12.55.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Nov 2025 12:55:49 -0800 (PST) Date: Mon, 3 Nov 2025 17:55:38 -0300 From: Geraldo Nascimento To: Bjorn Helgaas Cc: linux-rockchip@lists.infradead.org, Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski , Conor Dooley , Johan Jonker Subject: Re: [RFC PATCH 2/2] PCI: rockchip-host: drop wait on PERST# toggle Message-ID: References: <20251103181038.GA1814635@bhelgaas> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251103181038.GA1814635@bhelgaas> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251103_125550_883585_6E889ED9 X-CRM114-Status: GOOD ( 22.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Nov 03, 2025 at 12:10:38PM -0600, Bjorn Helgaas wrote: > On Mon, Nov 03, 2025 at 03:27:25AM -0300, Geraldo Nascimento wrote: > > With this change PCIe will complete link-training with a known quirky > > device - Samsung OEM PM981a SSD. This is completely against the PCIe > > spec and yet it works as long as the power regulator for 3v3 PCIe > > power is not defined as always-on or boot-on. > > What is against the spec? In what way is this SSD "known quirky"? Is > there a published erratum for it? Hi Bjorn! My proposed change itself is against the spec. This SSD is known to simply not complete initial link-training with Rockchip-IP PCIe. This is not officialy documented but based on reports across boards (like the Armbian one). I think it's the other way around though, it's the Rockchip-IP PCIe controller that is quirky somehow and doesn't play nice with many, many devices. > > Removing this delay might make this SSD work, but if this delay is > required per PCIe spec, how can we be confident that other devices > will still work? We really can't be sure there will be no side-effects to other devices. > > Reports of devices that still work is not really enough to move this > from the "hack that makes one device work" column to the "safe and > effective for all devices" column. I agree, and I knew from the start I would not get encouragements from the community relative to this change. Still, it seemed selfish not to share the workaround. > > It's easy to see how *lack* of a delay can break something, but much > harder to imagine how *removing* a delay can make something work. > Devices must be able to tolerate pretty much arbitrary delays. That said, the problem of quirky Rockchip-IP PCIe remains. The fact that removing the delay makes it work with devices that previously did not complete initial link training must at least point to a resolution somehow, even if the present change is unacceptable. I'll continue to hack around this, see if I can pinpoint exactly why that delay screws up my initial link training. Thanks, Geraldo Nascimento