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From: Niklas Cassel <cassel@kernel.org>
To: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Cc: Vincent Guittot <vincent.guittot@linaro.org>,
	Bjorn Helgaas <helgaas@kernel.org>,
	chester62515@gmail.com, mbrugger@suse.com,
	ghennadi.procopciuc@oss.nxp.com, s32@nxp.com,
	bhelgaas@google.com, jingoohan1@gmail.com, lpieralisi@kernel.org,
	kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org, Ionut.Vicovan@nxp.com,
	larisa.grigore@nxp.com, Ghennadi.Procopciuc@nxp.com,
	ciprianmarian.costea@nxp.com, bogdan.hamciuc@nxp.com,
	Frank.li@nxp.com, linux-arm-kernel@lists.infradead.org,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	LKML <linux-kernel@vger.kernel.org>,
	imx@lists.linux.dev
Subject: Re: [PATCH 3/4 v3] PCI: s32g: Add initial PCIe support (RC)
Date: Wed, 5 Nov 2025 12:00:11 +0100	[thread overview]
Message-ID: <aQsuO5WaYPK0KbVw@ryzen> (raw)
In-Reply-To: <bf3b2d2a-ce3e-87af-4154-abd022c6a3b4@linux.intel.com>

On Wed, Nov 05, 2025 at 12:43:09PM +0200, Ilpo Järvinen wrote:
> On Wed, 5 Nov 2025, Niklas Cassel wrote:
> 
> > On Fri, Oct 24, 2025 at 08:50:46AM +0200, Vincent Guittot wrote:
> > > On Wed, 22 Oct 2025 at 21:04, Bjorn Helgaas <helgaas@kernel.org> wrote:
> > > > > +     dw_pcie_dbi_ro_wr_en(pci);
> > > > > +
> > > > > +     val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE);
> > > > > +     val |= PORT_FORCE_DO_DESKEW_FOR_SRIS;
> > > > > +     dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val);
> > > > > +
> > > > > +     /*
> > > > > +      * Set max payload supported, 256 bytes and
> > > > > +      * relaxed ordering.
> > > > > +      */
> > > > > +     val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
> > > > > +     val &= ~(PCI_EXP_DEVCTL_RELAX_EN |
> > > > > +              PCI_EXP_DEVCTL_PAYLOAD |
> > > > > +              PCI_EXP_DEVCTL_READRQ);
> > > > > +     val |= PCI_EXP_DEVCTL_RELAX_EN |
> > > > > +            PCI_EXP_DEVCTL_PAYLOAD_256B |
> > > > > +            PCI_EXP_DEVCTL_READRQ_256B;
> > > > > +     dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
> > > >
> > > > MPS and relaxed ordering should be configured by the PCI core.  Is
> > > > there some s32g-specific restriction about these?
> > > 
> > > I will check with the team why they did that
> > 
> > Most likely, the reason is that, the PCI core does not set the MPS to the
> > maximum supported MPS for the root port.
> 
> PCI core set/doesn't set MPS based on config. Perhaps try with 
> CONFIG_PCIE_BUS_PERFORMANCE.

Sorry, I should have been more clear.

Since a lot of PCIe controller drivers have similar code to the above,
it is obvious that a lot of controller drivers want to increase the MPS
regardless of PCIE_BUS_* bus config value.

With the current PCI code, MPS for root ports will not be touched if
PCIE_BUS_TUNE_OFF or PCIE_BUS_DEFAULT.

After the above series, MPS for root ports will be set to max supported
also for PCIE_BUS_DEFAULT.


Kind regards,
Niklas


  reply	other threads:[~2025-11-05 11:00 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-22 17:43 [PATCH 0/4 v3] PCI: s32g: Add support for PCIe controller Vincent Guittot
2025-10-22 17:43 ` [PATCH 1/4 v3] dt-bindings: PCI: s32g: Add NXP " Vincent Guittot
2025-10-22 19:17   ` Frank Li
2025-10-24  6:58     ` Vincent Guittot
2025-11-06  0:00   ` Bjorn Helgaas
2025-11-06  7:51     ` Vincent Guittot
2025-11-06  7:12   ` Manivannan Sadhasivam
2025-11-06  8:09     ` Vincent Guittot
2025-11-06 17:38       ` Bjorn Helgaas
2025-11-10  9:14         ` Vincent Guittot
2025-10-22 17:43 ` [PATCH 2/4 v3] PCI: dw: Add more registers and bitfield definition Vincent Guittot
2025-10-22 17:43 ` [PATCH 3/4 v3] PCI: s32g: Add initial PCIe support (RC) Vincent Guittot
2025-10-22 19:04   ` Bjorn Helgaas
2025-10-24  6:50     ` Vincent Guittot
2025-11-05 10:28       ` Niklas Cassel
2025-11-05 10:43         ` Ilpo Järvinen
2025-11-05 11:00           ` Niklas Cassel [this message]
2025-11-06  0:05       ` Bjorn Helgaas
2025-11-06  6:24         ` Manivannan Sadhasivam
2025-11-06  7:50           ` Vincent Guittot
2025-11-14 10:05           ` Christian Bruel
2025-11-14 21:35             ` Bjorn Helgaas
2025-11-06  7:46         ` Vincent Guittot
2025-10-22 19:44   ` Frank Li
2025-10-24  6:53     ` Vincent Guittot
2025-11-05  7:58       ` Vincent Guittot
2025-11-06 17:23   ` Bjorn Helgaas
2025-11-06 17:33     ` Vincent Guittot
2025-10-22 17:43 ` [PATCH 4/4 v3] MAINTAINERS: Add MAINTAINER for NXP S32G PCIe driver Vincent Guittot
2025-10-22 19:20   ` Frank Li

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