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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251105_030019_760957_56217A6D X-CRM114-Status: GOOD ( 19.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Nov 05, 2025 at 12:43:09PM +0200, Ilpo Järvinen wrote: > On Wed, 5 Nov 2025, Niklas Cassel wrote: > > > On Fri, Oct 24, 2025 at 08:50:46AM +0200, Vincent Guittot wrote: > > > On Wed, 22 Oct 2025 at 21:04, Bjorn Helgaas wrote: > > > > > + dw_pcie_dbi_ro_wr_en(pci); > > > > > + > > > > > + val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE); > > > > > + val |= PORT_FORCE_DO_DESKEW_FOR_SRIS; > > > > > + dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val); > > > > > + > > > > > + /* > > > > > + * Set max payload supported, 256 bytes and > > > > > + * relaxed ordering. > > > > > + */ > > > > > + val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); > > > > > + val &= ~(PCI_EXP_DEVCTL_RELAX_EN | > > > > > + PCI_EXP_DEVCTL_PAYLOAD | > > > > > + PCI_EXP_DEVCTL_READRQ); > > > > > + val |= PCI_EXP_DEVCTL_RELAX_EN | > > > > > + PCI_EXP_DEVCTL_PAYLOAD_256B | > > > > > + PCI_EXP_DEVCTL_READRQ_256B; > > > > > + dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); > > > > > > > > MPS and relaxed ordering should be configured by the PCI core. Is > > > > there some s32g-specific restriction about these? > > > > > > I will check with the team why they did that > > > > Most likely, the reason is that, the PCI core does not set the MPS to the > > maximum supported MPS for the root port. > > PCI core set/doesn't set MPS based on config. Perhaps try with > CONFIG_PCIE_BUS_PERFORMANCE. Sorry, I should have been more clear. Since a lot of PCIe controller drivers have similar code to the above, it is obvious that a lot of controller drivers want to increase the MPS regardless of PCIE_BUS_* bus config value. With the current PCI code, MPS for root ports will not be touched if PCIE_BUS_TUNE_OFF or PCIE_BUS_DEFAULT. After the above series, MPS for root ports will be set to max supported also for PCIE_BUS_DEFAULT. Kind regards, Niklas