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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?Eg4KHE/GlMJB+YIGIm4lg1qcfI8Vxqf55qsxWcJ/FFN5ufVOVqgu2jmvEM22?= =?us-ascii?Q?2Io8B2/1qB46B5pygoTtbopLMGBySNONzcckbKwBU1+YoHNToQtxAePTnLtf?= =?us-ascii?Q?IOAOPEfTxBTli7eDb4+RksRBFg52ZjbZR61dcNuAZq0VgwjnT5f1IREmWi1R?= =?us-ascii?Q?GWLkbhALPyslnNZvyYK10Yo4S0jL330r5TlbcJaA3qWPSJN5RKp7MdUH1uBK?= =?us-ascii?Q?DCaNtulI4NaHclpN0DV5etBJ56se0+KQo/EwholISxjRz2p/f/uu7yaYfZCL?= =?us-ascii?Q?oNnmDEoix3m7BVd5GStgr1qXc4lYrVc74scoqHmdAKyO+OOSypKnBh1RjabN?= =?us-ascii?Q?0EtbaJ4DLxko29PfQ5nwIQw61EktYdzxmxJNI6tGmkFIzQj1BGIAmfLPfIhs?= =?us-ascii?Q?FnmNItIhvFpnQD7gLg+HlgUgJJ0jzhXP9b9HOGuiYI3xGZlOlU8S+YTl/06h?= =?us-ascii?Q?UtFxEi5P9qPg5MyUoRl49L/scfQR6QR//Kditb4KbNyAWQhhPY5YBfMey0iq?= =?us-ascii?Q?PRej1L7DPpUKYNSmM/oeYrblNjxU7/mpGnEXKUiRBmZFSnshJsoH7Hw1ZGGS?= =?us-ascii?Q?cwfu6YvocDUaPFNVRDIExyMekzzPzW+8wvx++IS3eQvqPaetkXUc5q2TZeH8?= =?us-ascii?Q?0bloEd/BYJzt80numye7lEeFoAdJHVzK40Ln07aNlVI5BtHXMgYWroTFHaFi?= =?us-ascii?Q?zhMAmdutaTRD5lTPmmeITQDIUvzg3eb+2Q2XwcJvKdfmyEHn+1BLkuGCkoFg?= =?us-ascii?Q?u26XoS/jpNmCsyJ2bfGiQo0+HQABglnXSrlaIHzgI4uNOthARdmMh+TPt22j?= =?us-ascii?Q?1SGQbcfjIn+a12JSsjsp4iY5zLTHSszlm4oKNJGv9fqBJpkvYIzgu7jZdGie?= =?us-ascii?Q?Zd4avS45Q+xIArWotlmD6lB6rpiLAp0RK1Mk4wflAHfhjkaSpYk2JGa+Fmt/?= =?us-ascii?Q?zGkMWDF0AXO6u0wmvadSBhqQeHXrecIj5GvZ0H9MF1/l4st1fiZ91n0FEj2j?= =?us-ascii?Q?ZGoV3wAxx5DnLYJee9iYXHQMqOQLG1VO9JUx+TZQsg2J06rLznjvReYUHkiF?= =?us-ascii?Q?JilKgPJtUBGVtmBhluJXoxziivylpl8iujjdP0efCPkd3o3WKABwSkj0FQF8?= =?us-ascii?Q?1IQaTNTyCIFgAAT3xsz1//IJW9qNlwM+lR1Ig/r33Ed4kysoTQAGc6x6eTyy?= =?us-ascii?Q?8Cc0JCMWydOH+cLzK6cEjjEwc4PpWokfcQLbg5ZcJjwRauEFCHMWtRJ0jrcz?= =?us-ascii?Q?B2JRNSwF9WqWmOF0ysOzG/nGvmUsQiK365ZJ9OKD002NGhOvtw7zbGiIbiLw?= =?us-ascii?Q?chimruhAqxoFvFckZB8ItrAbi5XIcHC2K+8yz/eHriWe/8Cu1nzXqvU+tNfE?= =?us-ascii?Q?/FfHdrfKXY42njaq5uiglXhFLt0jDIZhFbmE8X1qI++d+djLYoKuo42eHv42?= =?us-ascii?Q?vVw2Xg7+XfD8tGfXkLpGIfO7y/ga+bUyHxwHCMvykUzZRgWpqCjdMcaDcsFa?= =?us-ascii?Q?5nlysQ5qARiAc+K4Ej37Jme4RtBzbbDZ1V+Neryc/sKqvuM6n6RpzqkYg9La?= =?us-ascii?Q?jQgQdkhCgcJkIJrgx8I=3D?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: b85104a5-cac9-4352-a656-08de2174674d X-MS-Exchange-CrossTenant-AuthSource: DB9PR04MB9626.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2025 22:48:16.9318 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 3B6qfx8+XpgzmSwLZOGhsP8h/UOkgB+MQwcx/K5GndqhLroTSaMWbl4ituPMwLfUFeu2Z6D7qHkEPe50HVbuyQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB11599 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251111_144821_620621_BF37F5BA X-CRM114-Status: GOOD ( 27.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Nov 11, 2025 at 04:16:08PM -0600, Bjorn Helgaas wrote: > From: Bjorn Helgaas > > L1 PM Substates require the CLKREF# signal and may also require > device-specific support. If CLKREF# is not supported or driver support is > lacking, enabling L1.1 or L1.2 may cause errors when accessing devices, > e.g., > > nvme nvme0: controller is down; will reset: CSTS=0xffffffff, PCI_STATUS=0x10 > > If the kernel is built with CONFIG_PCIEASPM_POWER_SUPERSAVE=y or users > enable L1.x via sysfs, users may trip over these errors even if L1 > Substates haven't been enabled by firmware or the driver. > > To prevent such errors, disable advertising the L1 PM Substates unless the > driver sets "dw_pcie.l1ss_support" to indicate that it knows CLKREF# is > present and any device-specific configuration has been done. > > Set "dw_pcie.l1ss_support" in tegra194 (if DT includes the > "supports-clkreq' property) and qcom (for 2.7.0 controllers) so they can > continue to use L1 Substates. > > Based on Niklas's patch: > https://patch.msgid.link/20251017163252.598812-2-cassel@kernel.org > > Signed-off-by: Bjorn Helgaas > --- > .../pci/controller/dwc/pcie-designware-ep.c | 2 ++ > .../pci/controller/dwc/pcie-designware-host.c | 2 ++ > drivers/pci/controller/dwc/pcie-designware.c | 24 +++++++++++++++++++ > drivers/pci/controller/dwc/pcie-designware.h | 2 ++ > drivers/pci/controller/dwc/pcie-qcom.c | 2 ++ > drivers/pci/controller/dwc/pcie-tegra194.c | 3 +++ > 6 files changed, 35 insertions(+) > ... > > +void dw_pcie_config_l1ss(struct dw_pcie *pci) > +{ > + u16 l1ss; > + u32 l1ss_cap; > + > + if (!pci->l1ss_support) I think when l1ss_support true, need return. when l1ss_support false, need clean PCI_L1SS_CAP. Do your logic reverise? Frank > + return; > + > + l1ss = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); > + if (!l1ss) > + return; > + > + /* > + * Unless the driver claims "l1ss_support", don't advertise L1 PM > + * Substates because they require CLKREF# and possibly other > + * device-specific configuration. > + */ > + l1ss_cap = dw_pcie_readl_dbi(pci, l1ss + PCI_L1SS_CAP); > + l1ss_cap &= ~(PCI_L1SS_CAP_PCIPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_1 | > + PCI_L1SS_CAP_PCIPM_L1_2 | PCI_L1SS_CAP_ASPM_L1_2 | > + PCI_L1SS_CAP_L1_PM_SS); > + dw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, l1ss_cap); > +} > + > void dw_pcie_setup(struct dw_pcie *pci) > { > u32 val; > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index e995f692a1ec..8d14b1fe2280 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -516,6 +516,7 @@ struct dw_pcie { > int max_link_speed; > u8 n_fts[2]; > struct dw_edma_chip edma; > + bool l1ss_support; /* L1 PM Substates support */ > struct clk_bulk_data app_clks[DW_PCIE_NUM_APP_CLKS]; > struct clk_bulk_data core_clks[DW_PCIE_NUM_CORE_CLKS]; > struct reset_control_bulk_data app_rsts[DW_PCIE_NUM_APP_RSTS]; > @@ -573,6 +574,7 @@ int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, > int type, u64 parent_bus_addr, > u8 bar, size_t size); > void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index); > +void dw_pcie_config_l1ss(struct dw_pcie *pci); > void dw_pcie_setup(struct dw_pcie *pci); > void dw_pcie_iatu_detect(struct dw_pcie *pci); > int dw_pcie_edma_detect(struct dw_pcie *pci); > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 805edbbfe7eb..61c2f4e2f74d 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1067,6 +1067,8 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) > val &= ~REQ_NOT_ENTR_L1; > writel(val, pcie->parf + PARF_PM_CTRL); > > + pci->l1ss_support = true; > + > val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); > val |= EN; > writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c > index 10e74458e667..3934757baa30 100644 > --- a/drivers/pci/controller/dwc/pcie-tegra194.c > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c > @@ -703,6 +703,9 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie) > val |= (pcie->aspm_pwr_on_t << 19); > dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val); > > + if (pcie->supports_clkreq) > + pci->l1ss_support = true; > + > /* Program L0s and L1 entrance latencies */ > val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); > val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK; > -- > 2.43.0 >