[PATCH v6 0/11] PCI: imx6: Add a method to handle CLKREQ# override

[PATCH v6 0/11] PCI: imx6: Add a method to handle CLKREQ# override

[Richard Zhu]

Clock Request is a reference clock request signal as defined by the PCIe
Mini CEM and M.2 specification; Also used by L1 PM Substates. But it's
an optional signal added in PCIe CEM r4.0, sec 2. The CLKREQ# support is
relied on the exact hardware board and device designs.

Add supports-clkreq property to i.MX PCIe M.2 port since the CLKREQ#
signal would be driven active low on this M.2 connector by the add-in
card to requtest reference clock. And, the host bridge driver can enable
the ASPM L1 PM Substates support if this property present.

To support L1 PM Substates, add a callback to clear CLKREQ# override on
the boards that support CLKREQ# in the hardware designs.

Main changes in v6:
- Rebase to v6.18-rc1.
- Add the dts changes into the v6 version patch-set.
- Fix the i.MX95 refclk enable that was missed in the v5 series.
- Make i.MX95 refclk enable parallel to the others.
- Describe the potential CLKREQ# problem on i.MX95 19x19 EVK second
  slot in the commit, and emphasis the CLKREQ# issue is caused by the
  board and device hardware designs.

Main changes in v5:
- New create imx8mm_pcie_clkreq_override() and keep the original
  enable_ref_clk callback function.

Main changes in v4:
- To align the function name when add the CLKREQ# override clear, rename
imx8mm_pcie_enable_ref_clk(), clean up codes refer to Mani' suggestions.

Main changes in v3:
- Rebase to v6.17-rc1.
- Update the commit message refer to Bjorn's suggestions.

Main changes in v2:
- Update the commit message, and collect the reviewed-by tag.

[PATCH v6 01/11] arm64: dts: imx95-15x15-evk: Add supports-clkreq
[PATCH v6 02/11] arm64: dts: imx95-19x19-evk: Add supports-clkreq
[PATCH v6 03/11] arm64: dts: imx8mm-evk: Add supports-clkreq property
[PATCH v6 04/11] arm64: dts: imx8mp-evk: Add supports-clkreq property
[PATCH v6 05/11] arm64: dts: imx8mq-evk: Add supports-clkreq property
[PATCH v6 06/11] arm64: dts: imx8qm-mek: Add supports-clkreq property
[PATCH v6 07/11] arm64: dts: imx8qxp-mek: Add supports-clkreq
[PATCH v6 08/11] PCI: dwc: Invoke post_init in dw_pcie_resume_noirq()
[PATCH v6 09/11] PCI: imx6: Add a new imx8mm_pcie_clkreq_override()
[PATCH v6 10/11] PCI: imx6: Add CLKREQ# override to enable REFCLK for
[PATCH v6 11/11] PCI: imx6: Add a callback to clear CLKREQ# override

arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi     |  1 +
arch/arm64/boot/dts/freescale/imx8mp-evk.dts      |  1 +
arch/arm64/boot/dts/freescale/imx8mq-evk.dts      |  2 ++
arch/arm64/boot/dts/freescale/imx8qm-mek.dts      |  1 +
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts     |  1 +
arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts |  1 +
arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts |  1 +
drivers/pci/controller/dwc/pci-imx6.c             | 50 +++++++++++++++++++++++++++++++++++++++++++++++++-
drivers/pci/controller/dwc/pcie-designware-host.c |  3 +++
9 files changed, 60 insertions(+), 1 deletion(-)

[PATCH v6 01/11] arm64: dts: imx95-15x15-evk: Add supports-clkreq property to PCIe M.2 port

[Richard Zhu]

According to PCIe r6.1, sec 5.5.1.

The following rules define how the L1.1 and L1.2 substates are entered:
Both the Upstream and Downstream Ports must monitor the logical state of
the CLKREQ# signal.

Typical implement is using open drain, which connect RC's clkreq# to
EP's clkreq# together and pull up clkreq#.

imx95-15x15-evk matches this requirement, so add supports-clkreq to
allow PCIe device enter ASPM L1 Sub-State.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
index 148243470dd4a..3ee032c154fa3 100644
--- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
@@ -556,6 +556,7 @@ &pcie0 {
 	pinctrl-names = "default";
 	reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>;
 	vpcie-supply = <&reg_m2_pwr>;
+	supports-clkreq;
 	status = "okay";
 };
 
-- 
2.37.1

[PATCH v6 02/11] arm64: dts: imx95-19x19-evk: Add supports-clkreq property to PCIe M.2 port

[Richard Zhu]

According to PCIe r6.1, sec 5.5.1.

The following rules define how the L1.1 and L1.2 substates are entered:
Both the Upstream and Downstream Ports must monitor the logical state of
the CLKREQ# signal.

Typical implement is using open drain, which connect RC's clkreq# to
EP's clkreq# together and pull up clkreq#.

imx95-19x19-evk matches this requirement, so add supports-clkreq to
allow PCIe device enter ASPM L1 Sub-State.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
index 9f968feccef67..0f470d3eb9af4 100644
--- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
@@ -542,6 +542,7 @@ &pcie0 {
 	pinctrl-names = "default";
 	reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>;
 	vpcie-supply = <&reg_pcie0>;
+	supports-clkreq;
 	status = "okay";
 };
 
-- 
2.37.1

[PATCH v6 03/11] arm64: dts: imx8mm-evk: Add supports-clkreq property to PCIe M.2 port

[Richard Zhu]

According to PCIe r6.1, sec 5.5.1.

The following rules define how the L1.1 and L1.2 substates are entered:
Both the Upstream and Downstream Ports must monitor the logical state of
the CLKREQ# signal.

Typical implement is using open drain, which connect RC's clkreq# to
EP's clkreq# together and pull up clkreq#.

imx8mm-evk matches this requirement, so add supports-clkreq to allow
PCIe device enter ASPM L1 Sub-State.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index ff7ca20752309..6eab8a6001dbf 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -542,6 +542,7 @@ &pcie0 {
 	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
 				 <&clk IMX8MM_SYS_PLL2_250M>;
 	vpcie-supply = <&reg_pcie0>;
+	supports-clkreq;
 	status = "okay";
 };
 
-- 
2.37.1

[PATCH v6 04/11] arm64: dts: imx8mp-evk: Add supports-clkreq property to PCIe M.2 port

[Richard Zhu]

According to PCIe r6.1, sec 5.5.1.

The following rules define how the L1.1 and L1.2 substates are entered:
Both the Upstream and Downstream Ports must monitor the logical state of
the CLKREQ# signal.

Typical implement is using open drain, which connect RC's clkreq# to
EP's clkreq# together and pull up clkreq#.

imx8mp-evk matches this requirement, so add supports-clkreq to allow
PCIe device enter ASPM L1 Sub-State.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 3730792daf501..523bf4aeff317 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -710,6 +710,7 @@ &pcie0 {
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
 	vpcie-supply = <&reg_pcie0>;
+	supports-clkreq;
 	status = "okay";
 };
 
-- 
2.37.1

[PATCH v6 05/11] arm64: dts: imx8mq-evk: Add supports-clkreq property to PCIe M.2 port

[Richard Zhu]

According to PCIe r6.1, sec 5.5.1.

The following rules define how the L1.1 and L1.2 substates are entered:
Both the Upstream and Downstream Ports must monitor the logical state of
the CLKREQ# signal.

Typical implement is using open drain, which connect RC's clkreq# to
EP's clkreq# together and pull up clkreq#.

imx8mq-evk matches this requirement, so add supports-clkreq to allow
PCIe device enter ASPM L1 Sub-State.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index a88bc90346636..852992b915a39 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -375,6 +375,7 @@ &pcie0 {
 		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
 		 <&clk IMX8MQ_CLK_PCIE1_AUX>;
 	vph-supply = <&vgen5_reg>;
+	supports-clkreq;
 	status = "okay";
 };
 
@@ -398,6 +399,7 @@ &pcie1 {
 		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
 	vpcie-supply = <&reg_pcie1>;
 	vph-supply = <&vgen5_reg>;
+	supports-clkreq;
 	status = "okay";
 };
 
-- 
2.37.1

[PATCH v6 06/11] arm64: dts: imx8qm-mek: Add supports-clkreq property to PCIe M.2 port

[Richard Zhu]

According to PCIe r6.1, sec 5.5.1.

The following rules define how the L1.1 and L1.2 substates are entered:
Both the Upstream and Downstream Ports must monitor the logical state of
the CLKREQ# signal.

Typical implement is using open drain, which connect RC's clkreq# to
EP's clkreq# together and pull up clkreq#.

imx8qm-mek matches this requirement, so add supports-clkreq to allow
PCIe device enter ASPM L1 Sub-State.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 202d5c67ac40b..c1e4775c13849 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -775,6 +775,7 @@ &pciea {
 	pinctrl-names = "default";
 	reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
 	vpcie-supply = <&reg_pciea>;
+	supports-clkreq;
 	status = "okay";
 };
 
-- 
2.37.1

[PATCH v6 07/11] arm64: dts: imx8qxp-mek: Add supports-clkreq property to PCIe M.2 port

[Richard Zhu]

According to PCIe r6.1, sec 5.5.1.

The following rules define how the L1.1 and L1.2 substates are entered:
Both the Upstream and Downstream Ports must monitor the logical state of
the CLKREQ# signal.

Typical implement is using open drain, which connect RC's clkreq# to
EP's clkreq# together and pull up clkreq#.

imx8qxp-mek matches this requirement, so add supports-clkreq to allow
PCIe device enter ASPM L1 Sub-State.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 7b03374455410..9c457c2236a61 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -631,6 +631,7 @@ &pcie0 {
 	pinctrl-names = "default";
 	reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
 	vpcie-supply = <&reg_pcieb>;
+	supports-clkreq;
 	status = "okay";
 };
 
-- 
2.37.1

[PATCH v6 08/11] PCI: dwc: Invoke post_init in dw_pcie_resume_noirq()

[Richard Zhu]

If the ops has post_init callback, invoke it in dw_pcie_resume_noirq().

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 20c9333bcb1c4..2b59e7d2e6179 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -1199,6 +1199,9 @@ int dw_pcie_resume_noirq(struct dw_pcie *pci)
 	if (ret)
 		return ret;
 
+	if (pci->pp.ops->post_init)
+		pci->pp.ops->post_init(&pci->pp);
+
 	return ret;
 }
 EXPORT_SYMBOL_GPL(dw_pcie_resume_noirq);
-- 
2.37.1

[PATCH v6 09/11] PCI: imx6: Add a new imx8mm_pcie_clkreq_override() for i.MX8M PCIes

[Richard Zhu]

Add a new imx8mm_pcie_clkreq_override() for i.MX8M PCIes. Pave the path
to support L1 PM Substates after clear CLKREQ# override. No function
changes.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 4668fc9648bff..a60fe7c337e08 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -685,7 +685,7 @@ static int imx6q_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
 	return 0;
 }
 
-static int imx8mm_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
+static void imx8mm_pcie_clkreq_override(struct imx_pcie *imx_pcie, bool enable)
 {
 	int offset = imx_pcie_grp_offset(imx_pcie);
 
@@ -695,6 +695,11 @@ static int imx8mm_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
 	regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
 			   IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
 			   enable ? IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0);
+}
+
+static int imx8mm_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
+{
+	imx8mm_pcie_clkreq_override(imx_pcie, enable);
 	return 0;
 }
 
-- 
2.37.1

[PATCH v6 10/11] PCI: imx6: Add CLKREQ# override to enable REFCLK for i.MX95 PCIe

[Richard Zhu]

The CLKREQ# is an open drain, active low signal that is driven low by
the card to request reference clock. It's an optional signal added in
PCIe CEM r4.0, sec 2. Thus, this signal wouldn't be driven low if it's
reserved.

On i.MX95 EVK board, the PCIe slot connected to the second PCIe
controller is one standard PCIe slot. The default voltage of CLKREQ# is
not active low, and may not be driven to active low due to the potential
scenario listed above (e.x INTEL e1000e network card).

Since the reference clock controlled by CLKREQ# is required by i.MX95
PCIe host too. To make sure this clock is ready even when the CLKREQ#
isn't driven low by the card(e.x the scenario described above), force
CLKREQ# override active low for i.MX95 PCIe host to enable reference
clock.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index a60fe7c337e08..aa5a4900d0eb6 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -52,6 +52,8 @@
 #define IMX95_PCIE_REF_CLKEN			BIT(23)
 #define IMX95_PCIE_PHY_CR_PARA_SEL		BIT(9)
 #define IMX95_PCIE_SS_RW_REG_1			0xf4
+#define IMX95_PCIE_CLKREQ_OVERRIDE_EN		BIT(8)
+#define IMX95_PCIE_CLKREQ_OVERRIDE_VAL		BIT(9)
 #define IMX95_PCIE_SYS_AUX_PWR_DET		BIT(31)
 
 #define IMX95_PE0_GEN_CTRL_1			0x1050
@@ -711,6 +713,22 @@ static int imx7d_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
 	return 0;
 }
 
+static void  imx95_pcie_clkreq_override(struct imx_pcie *imx_pcie, bool enable)
+{
+	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1,
+			   IMX95_PCIE_CLKREQ_OVERRIDE_EN,
+			   enable ? IMX95_PCIE_CLKREQ_OVERRIDE_EN : 0);
+	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1,
+			   IMX95_PCIE_CLKREQ_OVERRIDE_VAL,
+			   enable ? IMX95_PCIE_CLKREQ_OVERRIDE_VAL : 0);
+}
+
+static int imx95_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
+{
+	imx95_pcie_clkreq_override(imx_pcie, enable);
+	return 0;
+}
+
 static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
 {
 	struct dw_pcie *pci = imx_pcie->pci;
@@ -1918,6 +1936,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
 		.core_reset = imx95_pcie_core_reset,
 		.init_phy = imx95_pcie_init_phy,
 		.wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
+		.enable_ref_clk = imx95_pcie_enable_ref_clk,
 	},
 	[IMX8MQ_EP] = {
 		.variant = IMX8MQ_EP,
@@ -1974,6 +1993,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
 		.core_reset = imx95_pcie_core_reset,
 		.wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
 		.epc_features = &imx95_pcie_epc_features,
+		.enable_ref_clk = imx95_pcie_enable_ref_clk,
 		.mode = DW_PCIE_EP_TYPE,
 	},
 };
-- 
2.37.1

[PATCH v6 11/11] PCI: imx6: Add a callback to clear CLKREQ# override

[Richard Zhu]

Clock Request is a reference clock request signal as defined by the PCIe
Mini CEM and M.2 specification; Also used by L1 PM Substates. But it's
an optional signal added in PCIe CEM r4.0, sec 2. The CLKREQ# support is
relied on the exact hardware board and device designs.

To support L1 PM Substates, add a callback to clear CLKREQ# override on
the boards that support CLKREQ# in the hardware designs.

The CLKREQ# override can be cleared safely when supports-clkreq is
present and PCIe link is up later. Because the CLKREQ# would be driven
low by the card at this time.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index aa5a4900d0eb6..7cd0dc62ffd3b 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -138,6 +138,7 @@ struct imx_pcie_drvdata {
 	int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable);
 	int (*core_reset)(struct imx_pcie *pcie, bool assert);
 	int (*wait_pll_lock)(struct imx_pcie *pcie);
+	void (*clr_clkreq_override)(struct imx_pcie *pcie);
 	const struct dw_pcie_host_ops *ops;
 };
 
@@ -151,6 +152,7 @@ struct imx_pcie {
 	struct gpio_desc	*reset_gpiod;
 	struct clk_bulk_data	*clks;
 	int			num_clks;
+	bool			supports_clkreq;
 	struct regmap		*iomuxc_gpr;
 	u16			msi_ctrl;
 	u32			controller_id;
@@ -729,6 +731,16 @@ static int imx95_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
 	return 0;
 }
 
+static void imx8mm_pcie_clr_clkreq_override(struct imx_pcie *imx_pcie)
+{
+	imx8mm_pcie_clkreq_override(imx_pcie, false);
+}
+
+static void imx95_pcie_clr_clkreq_override(struct imx_pcie *imx_pcie)
+{
+	imx95_pcie_clkreq_override(imx_pcie, false);
+}
+
 static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
 {
 	struct dw_pcie *pci = imx_pcie->pci;
@@ -1345,6 +1357,12 @@ static void imx_pcie_host_post_init(struct dw_pcie_rp *pp)
 		dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
 		dw_pcie_dbi_ro_wr_dis(pci);
 	}
+
+	/* Clear CLKREQ# override if supports_clkreq is true and link is up */
+	if (dw_pcie_link_up(pci) && imx_pcie->supports_clkreq) {
+		if (imx_pcie->drvdata->clr_clkreq_override)
+			imx_pcie->drvdata->clr_clkreq_override(imx_pcie);
+	}
 }
 
 /*
@@ -1763,6 +1781,7 @@ static int imx_pcie_probe(struct platform_device *pdev)
 	/* Limit link speed */
 	pci->max_link_speed = 1;
 	of_property_read_u32(node, "fsl,max-link-speed", &pci->max_link_speed);
+	imx_pcie->supports_clkreq = of_property_read_bool(node, "supports-clkreq");
 
 	ret = devm_regulator_get_enable_optional(&pdev->dev, "vpcie3v3aux");
 	if (ret < 0 && ret != -ENODEV)
@@ -1896,6 +1915,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
 		.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
 		.init_phy = imx8mq_pcie_init_phy,
 		.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
+		.clr_clkreq_override = imx8mm_pcie_clr_clkreq_override,
 	},
 	[IMX8MM] = {
 		.variant = IMX8MM,
@@ -1906,6 +1926,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
 		.mode_off[0] = IOMUXC_GPR12,
 		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
 		.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
+		.clr_clkreq_override = imx8mm_pcie_clr_clkreq_override,
 	},
 	[IMX8MP] = {
 		.variant = IMX8MP,
@@ -1916,6 +1937,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
 		.mode_off[0] = IOMUXC_GPR12,
 		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
 		.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
+		.clr_clkreq_override = imx8mm_pcie_clr_clkreq_override,
 	},
 	[IMX8Q] = {
 		.variant = IMX8Q,
@@ -1937,6 +1959,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
 		.init_phy = imx95_pcie_init_phy,
 		.wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
 		.enable_ref_clk = imx95_pcie_enable_ref_clk,
+		.clr_clkreq_override = imx95_pcie_clr_clkreq_override,
 	},
 	[IMX8MQ_EP] = {
 		.variant = IMX8MQ_EP,
-- 
2.37.1

Re: [PATCH v6 10/11] PCI: imx6: Add CLKREQ# override to enable REFCLK for i.MX95 PCIe

[Alexander Stein]

Hi,

Am Mittwoch, 15. Oktober 2025, 05:04:27 CET schrieb Richard Zhu:
> The CLKREQ# is an open drain, active low signal that is driven low by
> the card to request reference clock. It's an optional signal added in
> PCIe CEM r4.0, sec 2. Thus, this signal wouldn't be driven low if it's
> reserved.
> 
> On i.MX95 EVK board, the PCIe slot connected to the second PCIe
> controller is one standard PCIe slot. The default voltage of CLKREQ# is
> not active low, and may not be driven to active low due to the potential
> scenario listed above (e.x INTEL e1000e network card).
> 
> Since the reference clock controlled by CLKREQ# is required by i.MX95
> PCIe host too. To make sure this clock is ready even when the CLKREQ#
> isn't driven low by the card(e.x the scenario described above), force
> CLKREQ# override active low for i.MX95 PCIe host to enable reference
> clock.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>

Thanks, this is actually required on TQMa95xxSA.
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>

> ---
>  drivers/pci/controller/dwc/pci-imx6.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index a60fe7c337e08..aa5a4900d0eb6 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -52,6 +52,8 @@
>  #define IMX95_PCIE_REF_CLKEN			BIT(23)
>  #define IMX95_PCIE_PHY_CR_PARA_SEL		BIT(9)
>  #define IMX95_PCIE_SS_RW_REG_1			0xf4
> +#define IMX95_PCIE_CLKREQ_OVERRIDE_EN		BIT(8)
> +#define IMX95_PCIE_CLKREQ_OVERRIDE_VAL		BIT(9)
>  #define IMX95_PCIE_SYS_AUX_PWR_DET		BIT(31)
>  
>  #define IMX95_PE0_GEN_CTRL_1			0x1050
> @@ -711,6 +713,22 @@ static int imx7d_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
>  	return 0;
>  }
>  
> +static void  imx95_pcie_clkreq_override(struct imx_pcie *imx_pcie, bool enable)
> +{
> +	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1,
> +			   IMX95_PCIE_CLKREQ_OVERRIDE_EN,
> +			   enable ? IMX95_PCIE_CLKREQ_OVERRIDE_EN : 0);
> +	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1,
> +			   IMX95_PCIE_CLKREQ_OVERRIDE_VAL,
> +			   enable ? IMX95_PCIE_CLKREQ_OVERRIDE_VAL : 0);
> +}
> +
> +static int imx95_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
> +{
> +	imx95_pcie_clkreq_override(imx_pcie, enable);
> +	return 0;
> +}
> +
>  static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
>  {
>  	struct dw_pcie *pci = imx_pcie->pci;
> @@ -1918,6 +1936,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
>  		.core_reset = imx95_pcie_core_reset,
>  		.init_phy = imx95_pcie_init_phy,
>  		.wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
> +		.enable_ref_clk = imx95_pcie_enable_ref_clk,
>  	},
>  	[IMX8MQ_EP] = {
>  		.variant = IMX8MQ_EP,
> @@ -1974,6 +1993,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
>  		.core_reset = imx95_pcie_core_reset,
>  		.wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
>  		.epc_features = &imx95_pcie_epc_features,
> +		.enable_ref_clk = imx95_pcie_enable_ref_clk,
>  		.mode = DW_PCIE_EP_TYPE,
>  	},
>  };
> 


-- 
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/

Re: [PATCH v6 01/11] arm64: dts: imx95-15x15-evk: Add supports-clkreq property to PCIe M.2 port

[Frank Li]

On Wed, Oct 15, 2025 at 11:04:18AM +0800, Richard Zhu wrote:
> According to PCIe r6.1, sec 5.5.1.
>
> The following rules define how the L1.1 and L1.2 substates are entered:
> Both the Upstream and Downstream Ports must monitor the logical state of
> the CLKREQ# signal.
>
> Typical implement is using open drain, which connect RC's clkreq# to
> EP's clkreq# together and pull up clkreq#.
>
> imx95-15x15-evk matches this requirement, so add supports-clkreq to
> allow PCIe device enter ASPM L1 Sub-State.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> ---
>  arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> index 148243470dd4a..3ee032c154fa3 100644
> --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> @@ -556,6 +556,7 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>;
>  	vpcie-supply = <&reg_m2_pwr>;
> +	supports-clkreq;
>  	status = "okay";
>  };
>
> --
> 2.37.1
>

Re: [PATCH v6 02/11] arm64: dts: imx95-19x19-evk: Add supports-clkreq property to PCIe M.2 port

[Frank Li]

On Wed, Oct 15, 2025 at 11:04:19AM +0800, Richard Zhu wrote:
> According to PCIe r6.1, sec 5.5.1.
>
> The following rules define how the L1.1 and L1.2 substates are entered:
> Both the Upstream and Downstream Ports must monitor the logical state of
> the CLKREQ# signal.
>
> Typical implement is using open drain, which connect RC's clkreq# to
> EP's clkreq# together and pull up clkreq#.
>
> imx95-19x19-evk matches this requirement, so add supports-clkreq to
> allow PCIe device enter ASPM L1 Sub-State.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
> index 9f968feccef67..0f470d3eb9af4 100644
> --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
> @@ -542,6 +542,7 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>;
>  	vpcie-supply = <&reg_pcie0>;
> +	supports-clkreq;
>  	status = "okay";
>  };
>
> --
> 2.37.1
>

Re: [PATCH v6 03/11] arm64: dts: imx8mm-evk: Add supports-clkreq property to PCIe M.2 port

[Frank Li]

On Wed, Oct 15, 2025 at 11:04:20AM +0800, Richard Zhu wrote:
> According to PCIe r6.1, sec 5.5.1.
>
> The following rules define how the L1.1 and L1.2 substates are entered:
> Both the Upstream and Downstream Ports must monitor the logical state of
> the CLKREQ# signal.
>
> Typical implement is using open drain, which connect RC's clkreq# to
> EP's clkreq# together and pull up clkreq#.
>
> imx8mm-evk matches this requirement, so add supports-clkreq to allow
> PCIe device enter ASPM L1 Sub-State.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> index ff7ca20752309..6eab8a6001dbf 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> @@ -542,6 +542,7 @@ &pcie0 {
>  	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
>  				 <&clk IMX8MM_SYS_PLL2_250M>;
>  	vpcie-supply = <&reg_pcie0>;
> +	supports-clkreq;
>  	status = "okay";
>  };
>
> --
> 2.37.1
>

Re: [PATCH v6 04/11] arm64: dts: imx8mp-evk: Add supports-clkreq property to PCIe M.2 port

[Frank Li]

On Wed, Oct 15, 2025 at 11:04:21AM +0800, Richard Zhu wrote:
> According to PCIe r6.1, sec 5.5.1.
>
> The following rules define how the L1.1 and L1.2 substates are entered:
> Both the Upstream and Downstream Ports must monitor the logical state of
> the CLKREQ# signal.
>
> Typical implement is using open drain, which connect RC's clkreq# to
> EP's clkreq# together and pull up clkreq#.
>
> imx8mp-evk matches this requirement, so add supports-clkreq to allow
> PCIe device enter ASPM L1 Sub-State.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> index 3730792daf501..523bf4aeff317 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> @@ -710,6 +710,7 @@ &pcie0 {
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>;
>  	vpcie-supply = <&reg_pcie0>;
> +	supports-clkreq;
>  	status = "okay";
>  };
>
> --
> 2.37.1
>

Re: [PATCH v6 05/11] arm64: dts: imx8mq-evk: Add supports-clkreq property to PCIe M.2 port

[Frank Li]

On Wed, Oct 15, 2025 at 11:04:22AM +0800, Richard Zhu wrote:
> According to PCIe r6.1, sec 5.5.1.
>
> The following rules define how the L1.1 and L1.2 substates are entered:
> Both the Upstream and Downstream Ports must monitor the logical state of
> the CLKREQ# signal.
>
> Typical implement is using open drain, which connect RC's clkreq# to
> EP's clkreq# together and pull up clkreq#.
>
> imx8mq-evk matches this requirement, so add supports-clkreq to allow
> PCIe device enter ASPM L1 Sub-State.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> index a88bc90346636..852992b915a39 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> @@ -375,6 +375,7 @@ &pcie0 {
>  		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
>  		 <&clk IMX8MQ_CLK_PCIE1_AUX>;
>  	vph-supply = <&vgen5_reg>;
> +	supports-clkreq;
>  	status = "okay";
>  };
>
> @@ -398,6 +399,7 @@ &pcie1 {
>  		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
>  	vpcie-supply = <&reg_pcie1>;
>  	vph-supply = <&vgen5_reg>;
> +	supports-clkreq;
>  	status = "okay";
>  };
>
> --
> 2.37.1
>

Re: [PATCH v6 06/11] arm64: dts: imx8qm-mek: Add supports-clkreq property to PCIe M.2 port

[Frank Li]

On Wed, Oct 15, 2025 at 11:04:23AM +0800, Richard Zhu wrote:
> According to PCIe r6.1, sec 5.5.1.
>
> The following rules define how the L1.1 and L1.2 substates are entered:
> Both the Upstream and Downstream Ports must monitor the logical state of
> the CLKREQ# signal.
>
> Typical implement is using open drain, which connect RC's clkreq# to
> EP's clkreq# together and pull up clkreq#.
>
> imx8qm-mek matches this requirement, so add supports-clkreq to allow
> PCIe device enter ASPM L1 Sub-State.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

shawn: I posted it as richard at imx8qm dts patches, you can pick this one
with other part together.

>  arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> index 202d5c67ac40b..c1e4775c13849 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
> @@ -775,6 +775,7 @@ &pciea {
>  	pinctrl-names = "default";
>  	reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
>  	vpcie-supply = <&reg_pciea>;
> +	supports-clkreq;
>  	status = "okay";
>  };
>
> --
> 2.37.1
>

Re: [PATCH v6 07/11] arm64: dts: imx8qxp-mek: Add supports-clkreq property to PCIe M.2 port

[Frank Li]

On Wed, Oct 15, 2025 at 11:04:24AM +0800, Richard Zhu wrote:
> According to PCIe r6.1, sec 5.5.1.
>
> The following rules define how the L1.1 and L1.2 substates are entered:
> Both the Upstream and Downstream Ports must monitor the logical state of
> the CLKREQ# signal.
>
> Typical implement is using open drain, which connect RC's clkreq# to
> EP's clkreq# together and pull up clkreq#.
>
> imx8qxp-mek matches this requirement, so add supports-clkreq to allow
> PCIe device enter ASPM L1 Sub-State.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

shawn: I posted it as richard at imx8qxp dts patches, you can pick this one
with other part together.

>  arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> index 7b03374455410..9c457c2236a61 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> @@ -631,6 +631,7 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
>  	vpcie-supply = <&reg_pcieb>;
> +	supports-clkreq;
>  	status = "okay";
>  };
>
> --
> 2.37.1
>

Re: [PATCH v6 09/11] PCI: imx6: Add a new imx8mm_pcie_clkreq_override() for i.MX8M PCIes

[Frank Li]

On Wed, Oct 15, 2025 at 11:04:26AM +0800, Richard Zhu wrote:
> Add a new imx8mm_pcie_clkreq_override() for i.MX8M PCIes. Pave the path
> to support L1 PM Substates after clear CLKREQ# override. No function
> changes.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> ---
>  drivers/pci/controller/dwc/pci-imx6.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 4668fc9648bff..a60fe7c337e08 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -685,7 +685,7 @@ static int imx6q_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
>  	return 0;
>  }
>
> -static int imx8mm_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
> +static void imx8mm_pcie_clkreq_override(struct imx_pcie *imx_pcie, bool enable)
>  {
>  	int offset = imx_pcie_grp_offset(imx_pcie);
>
> @@ -695,6 +695,11 @@ static int imx8mm_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
>  	regmap_update_bits(imx_pcie->iomuxc_gpr, offset,
>  			   IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
>  			   enable ? IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0);
> +}
> +
> +static int imx8mm_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
> +{
> +	imx8mm_pcie_clkreq_override(imx_pcie, enable);
>  	return 0;
>  }
>
> --
> 2.37.1
>

Re: [PATCH v6 11/11] PCI: imx6: Add a callback to clear CLKREQ# override

[Frank Li]

On Wed, Oct 15, 2025 at 11:04:28AM +0800, Richard Zhu wrote:
> Clock Request is a reference clock request signal as defined by the PCIe
> Mini CEM and M.2 specification; Also used by L1 PM Substates. But it's
> an optional signal added in PCIe CEM r4.0, sec 2. The CLKREQ# support is
> relied on the exact hardware board and device designs.
>
> To support L1 PM Substates, add a callback to clear CLKREQ# override on
> the boards that support CLKREQ# in the hardware designs.
>
> The CLKREQ# override can be cleared safely when supports-clkreq is
> present and PCIe link is up later. Because the CLKREQ# would be driven
> low by the card at this time.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
>  drivers/pci/controller/dwc/pci-imx6.c | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index aa5a4900d0eb6..7cd0dc62ffd3b 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -138,6 +138,7 @@ struct imx_pcie_drvdata {
>  	int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable);
>  	int (*core_reset)(struct imx_pcie *pcie, bool assert);
>  	int (*wait_pll_lock)(struct imx_pcie *pcie);
> +	void (*clr_clkreq_override)(struct imx_pcie *pcie);
>  	const struct dw_pcie_host_ops *ops;
>  };
>
> @@ -151,6 +152,7 @@ struct imx_pcie {
>  	struct gpio_desc	*reset_gpiod;
>  	struct clk_bulk_data	*clks;
>  	int			num_clks;
> +	bool			supports_clkreq;
>  	struct regmap		*iomuxc_gpr;
>  	u16			msi_ctrl;
>  	u32			controller_id;
> @@ -729,6 +731,16 @@ static int imx95_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
>  	return 0;
>  }
>
> +static void imx8mm_pcie_clr_clkreq_override(struct imx_pcie *imx_pcie)
> +{
> +	imx8mm_pcie_clkreq_override(imx_pcie, false);
> +}
> +
> +static void imx95_pcie_clr_clkreq_override(struct imx_pcie *imx_pcie)
> +{
> +	imx95_pcie_clkreq_override(imx_pcie, false);
> +}
> +
>  static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
>  {
>  	struct dw_pcie *pci = imx_pcie->pci;
> @@ -1345,6 +1357,12 @@ static void imx_pcie_host_post_init(struct dw_pcie_rp *pp)
>  		dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
>  		dw_pcie_dbi_ro_wr_dis(pci);
>  	}
> +
> +	/* Clear CLKREQ# override if supports_clkreq is true and link is up */
> +	if (dw_pcie_link_up(pci) && imx_pcie->supports_clkreq) {
> +		if (imx_pcie->drvdata->clr_clkreq_override)
> +			imx_pcie->drvdata->clr_clkreq_override(imx_pcie);
> +	}

Does below codes look more clear?

	if (!dw_pcie_link_up(pci))
		return;

	if (mx_pcie->drvdata->clr_clkreq_override && imx_pcie->supports_clkreq)
		imx_pcie->drvdata->clr_clkreq_override(imx_pcie);

Frank
>  }
>
>  /*
> @@ -1763,6 +1781,7 @@ static int imx_pcie_probe(struct platform_device *pdev)
>  	/* Limit link speed */
>  	pci->max_link_speed = 1;
>  	of_property_read_u32(node, "fsl,max-link-speed", &pci->max_link_speed);
> +	imx_pcie->supports_clkreq = of_property_read_bool(node, "supports-clkreq");
>
>  	ret = devm_regulator_get_enable_optional(&pdev->dev, "vpcie3v3aux");
>  	if (ret < 0 && ret != -ENODEV)
> @@ -1896,6 +1915,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
>  		.mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
>  		.init_phy = imx8mq_pcie_init_phy,
>  		.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
> +		.clr_clkreq_override = imx8mm_pcie_clr_clkreq_override,
>  	},
>  	[IMX8MM] = {
>  		.variant = IMX8MM,
> @@ -1906,6 +1926,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
>  		.mode_off[0] = IOMUXC_GPR12,
>  		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
>  		.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
> +		.clr_clkreq_override = imx8mm_pcie_clr_clkreq_override,
>  	},
>  	[IMX8MP] = {
>  		.variant = IMX8MP,
> @@ -1916,6 +1937,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
>  		.mode_off[0] = IOMUXC_GPR12,
>  		.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
>  		.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
> +		.clr_clkreq_override = imx8mm_pcie_clr_clkreq_override,
>  	},
>  	[IMX8Q] = {
>  		.variant = IMX8Q,
> @@ -1937,6 +1959,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
>  		.init_phy = imx95_pcie_init_phy,
>  		.wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
>  		.enable_ref_clk = imx95_pcie_enable_ref_clk,
> +		.clr_clkreq_override = imx95_pcie_clr_clkreq_override,
>  	},
>  	[IMX8MQ_EP] = {
>  		.variant = IMX8MQ_EP,
> --
> 2.37.1
>

Re: [PATCH v6 10/11] PCI: imx6: Add CLKREQ# override to enable REFCLK for i.MX95 PCIe

[Frank Li]

On Wed, Oct 15, 2025 at 11:04:27AM +0800, Richard Zhu wrote:
> The CLKREQ# is an open drain, active low signal that is driven low by
> the card to request reference clock. It's an optional signal added in
> PCIe CEM r4.0, sec 2. Thus, this signal wouldn't be driven low if it's
> reserved.
>
> On i.MX95 EVK board, the PCIe slot connected to the second PCIe
> controller is one standard PCIe slot. The default voltage of CLKREQ# is
> not active low, and may not be driven to active low due to the potential
> scenario listed above (e.x INTEL e1000e network card).
>
> Since the reference clock controlled by CLKREQ# is required by i.MX95
> PCIe host too. To make sure this clock is ready even when the CLKREQ#
> isn't driven low by the card(e.x the scenario described above), force
> CLKREQ# override active low for i.MX95 PCIe host to enable reference
> clock.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  drivers/pci/controller/dwc/pci-imx6.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index a60fe7c337e08..aa5a4900d0eb6 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -52,6 +52,8 @@
>  #define IMX95_PCIE_REF_CLKEN			BIT(23)
>  #define IMX95_PCIE_PHY_CR_PARA_SEL		BIT(9)
>  #define IMX95_PCIE_SS_RW_REG_1			0xf4
> +#define IMX95_PCIE_CLKREQ_OVERRIDE_EN		BIT(8)
> +#define IMX95_PCIE_CLKREQ_OVERRIDE_VAL		BIT(9)
>  #define IMX95_PCIE_SYS_AUX_PWR_DET		BIT(31)
>
>  #define IMX95_PE0_GEN_CTRL_1			0x1050
> @@ -711,6 +713,22 @@ static int imx7d_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
>  	return 0;
>  }
>
> +static void  imx95_pcie_clkreq_override(struct imx_pcie *imx_pcie, bool enable)
> +{
> +	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1,
> +			   IMX95_PCIE_CLKREQ_OVERRIDE_EN,
> +			   enable ? IMX95_PCIE_CLKREQ_OVERRIDE_EN : 0);
> +	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1,
> +			   IMX95_PCIE_CLKREQ_OVERRIDE_VAL,
> +			   enable ? IMX95_PCIE_CLKREQ_OVERRIDE_VAL : 0);
> +}
> +
> +static int imx95_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable)
> +{
> +	imx95_pcie_clkreq_override(imx_pcie, enable);
> +	return 0;
> +}
> +
>  static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie)
>  {
>  	struct dw_pcie *pci = imx_pcie->pci;
> @@ -1918,6 +1936,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
>  		.core_reset = imx95_pcie_core_reset,
>  		.init_phy = imx95_pcie_init_phy,
>  		.wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
> +		.enable_ref_clk = imx95_pcie_enable_ref_clk,
>  	},
>  	[IMX8MQ_EP] = {
>  		.variant = IMX8MQ_EP,
> @@ -1974,6 +1993,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
>  		.core_reset = imx95_pcie_core_reset,
>  		.wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
>  		.epc_features = &imx95_pcie_epc_features,
> +		.enable_ref_clk = imx95_pcie_enable_ref_clk,
>  		.mode = DW_PCIE_EP_TYPE,
>  	},
>  };
> --
> 2.37.1
>

Re: [PATCH v6 01/11] arm64: dts: imx95-15x15-evk: Add supports-clkreq property to PCIe M.2 port

[Shawn Guo]

On Wed, Oct 15, 2025 at 11:04:18AM +0800, Richard Zhu wrote:
> According to PCIe r6.1, sec 5.5.1.
> 
> The following rules define how the L1.1 and L1.2 substates are entered:
> Both the Upstream and Downstream Ports must monitor the logical state of
> the CLKREQ# signal.
> 
> Typical implement is using open drain, which connect RC's clkreq# to
> EP's clkreq# together and pull up clkreq#.
> 
> imx95-15x15-evk matches this requirement, so add supports-clkreq to
> allow PCIe device enter ASPM L1 Sub-State.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> index 148243470dd4a..3ee032c154fa3 100644
> --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> @@ -556,6 +556,7 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>;
>  	vpcie-supply = <&reg_m2_pwr>;
> +	supports-clkreq;

Is binding updated for this property?

Shawn

>  	status = "okay";
>  };
>  
> -- 
> 2.37.1
> 

RE: [PATCH v6 01/11] arm64: dts: imx95-15x15-evk: Add supports-clkreq property to PCIe M.2 port

[Hongxing Zhu]

> -----Original Message-----
> From: Shawn Guo <shawnguo2@yeah.net>
> Sent: 2025年11月11日 15:11
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
> lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;
> robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
> bhelgaas@google.com; shawnguo@kernel.org; s.hauer@pengutronix.de;
> kernel@pengutronix.de; festevam@gmail.com; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> imx@lists.linux.dev; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v6 01/11] arm64: dts: imx95-15x15-evk: Add
> supports-clkreq property to PCIe M.2 port
> 
> On Wed, Oct 15, 2025 at 11:04:18AM +0800, Richard Zhu wrote:
> > According to PCIe r6.1, sec 5.5.1.
> >
> > The following rules define how the L1.1 and L1.2 substates are entered:
> > Both the Upstream and Downstream Ports must monitor the logical state
> > of the CLKREQ# signal.
> >
> > Typical implement is using open drain, which connect RC's clkreq# to
> > EP's clkreq# together and pull up clkreq#.
> >
> > imx95-15x15-evk matches this requirement, so add supports-clkreq to
> > allow PCIe device enter ASPM L1 Sub-State.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> > b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> > index 148243470dd4a..3ee032c154fa3 100644
> > --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> > @@ -556,6 +556,7 @@ &pcie0 {
> >  	pinctrl-names = "default";
> >  	reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>;
> >  	vpcie-supply = <&reg_m2_pwr>;
> > +	supports-clkreq;
> 
> Is binding updated for this property?
> 
> Shawn
> 
Hi Shawn:
As I know that It's a documented binding property as below.
- supports-clkreq:
   If present this property specifies that CLKREQ signal routing exists from
   root port to downstream device and host bridge drivers can do programming
   which depends on CLKREQ signal existence. For example, programming root port
   not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
./Documentation/devicetree/bindings/pci/pci.txt

Best Regards
Richard Zhu

> >  	status = "okay";
> >  };
> >
> > --
> > 2.37.1
> >

Re: [PATCH v6 01/11] arm64: dts: imx95-15x15-evk: Add supports-clkreq property to PCIe M.2 port

[Frank Li]

On Tue, Nov 11, 2025 at 08:02:35AM +0000, Hongxing Zhu wrote:
> > -----Original Message-----
> > From: Shawn Guo <shawnguo2@yeah.net>
> > Sent: 2025年11月11日 15:11
> > To: Hongxing Zhu <hongxing.zhu@nxp.com>
> > Cc: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
> > lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;
> > robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
> > bhelgaas@google.com; shawnguo@kernel.org; s.hauer@pengutronix.de;
> > kernel@pengutronix.de; festevam@gmail.com; linux-pci@vger.kernel.org;
> > linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> > imx@lists.linux.dev; linux-kernel@vger.kernel.org
> > Subject: Re: [PATCH v6 01/11] arm64: dts: imx95-15x15-evk: Add
> > supports-clkreq property to PCIe M.2 port
> >
> > On Wed, Oct 15, 2025 at 11:04:18AM +0800, Richard Zhu wrote:
> > > According to PCIe r6.1, sec 5.5.1.
> > >
> > > The following rules define how the L1.1 and L1.2 substates are entered:
> > > Both the Upstream and Downstream Ports must monitor the logical state
> > > of the CLKREQ# signal.
> > >
> > > Typical implement is using open drain, which connect RC's clkreq# to
> > > EP's clkreq# together and pull up clkreq#.
> > >
> > > imx95-15x15-evk matches this requirement, so add supports-clkreq to
> > > allow PCIe device enter ASPM L1 Sub-State.
> > >
> > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > > ---
> > >  arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> > > b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> > > index 148243470dd4a..3ee032c154fa3 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> > > +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> > > @@ -556,6 +556,7 @@ &pcie0 {
> > >  	pinctrl-names = "default";
> > >  	reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>;
> > >  	vpcie-supply = <&reg_m2_pwr>;
> > > +	supports-clkreq;
> >
> > Is binding updated for this property?
> >
> > Shawn
> >
> Hi Shawn:
> As I know that It's a documented binding property as below.
> - supports-clkreq:
>    If present this property specifies that CLKREQ signal routing exists from
>    root port to downstream device and host bridge drivers can do programming
>    which depends on CLKREQ signal existence. For example, programming root port
>    not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
> ./Documentation/devicetree/bindings/pci/pci.txt

Shawn:

	This file should be removed. It is already merge to Rob's dt-scheme
as PCIe standard properties.

See: https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/pci/pci-bus-common.yaml

Frank

>
> Best Regards
> Richard Zhu
>
> > >  	status = "okay";
> > >  };
> > >
> > > --
> > > 2.37.1
> > >
>

Re: [PATCH v6 01/11] arm64: dts: imx95-15x15-evk: Add supports-clkreq property to PCIe M.2 port

[Shawn Guo]

On Tue, Nov 11, 2025 at 11:10:05AM -0500, Frank Li wrote:
> On Tue, Nov 11, 2025 at 08:02:35AM +0000, Hongxing Zhu wrote:
> > > -----Original Message-----
> > > From: Shawn Guo <shawnguo2@yeah.net>
> > > Sent: 2025年11月11日 15:11
> > > To: Hongxing Zhu <hongxing.zhu@nxp.com>
> > > Cc: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
> > > lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;
> > > robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
> > > bhelgaas@google.com; shawnguo@kernel.org; s.hauer@pengutronix.de;
> > > kernel@pengutronix.de; festevam@gmail.com; linux-pci@vger.kernel.org;
> > > linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> > > imx@lists.linux.dev; linux-kernel@vger.kernel.org
> > > Subject: Re: [PATCH v6 01/11] arm64: dts: imx95-15x15-evk: Add
> > > supports-clkreq property to PCIe M.2 port
> > >
> > > On Wed, Oct 15, 2025 at 11:04:18AM +0800, Richard Zhu wrote:
> > > > According to PCIe r6.1, sec 5.5.1.
> > > >
> > > > The following rules define how the L1.1 and L1.2 substates are entered:
> > > > Both the Upstream and Downstream Ports must monitor the logical state
> > > > of the CLKREQ# signal.
> > > >
> > > > Typical implement is using open drain, which connect RC's clkreq# to
> > > > EP's clkreq# together and pull up clkreq#.
> > > >
> > > > imx95-15x15-evk matches this requirement, so add supports-clkreq to
> > > > allow PCIe device enter ASPM L1 Sub-State.
> > > >
> > > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > > > ---
> > > >  arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 1 +
> > > >  1 file changed, 1 insertion(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> > > > b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> > > > index 148243470dd4a..3ee032c154fa3 100644
> > > > --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> > > > +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> > > > @@ -556,6 +556,7 @@ &pcie0 {
> > > >  	pinctrl-names = "default";
> > > >  	reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>;
> > > >  	vpcie-supply = <&reg_m2_pwr>;
> > > > +	supports-clkreq;
> > >
> > > Is binding updated for this property?
> > >
> > > Shawn
> > >
> > Hi Shawn:
> > As I know that It's a documented binding property as below.
> > - supports-clkreq:
> >    If present this property specifies that CLKREQ signal routing exists from
> >    root port to downstream device and host bridge drivers can do programming
> >    which depends on CLKREQ signal existence. For example, programming root port
> >    not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
> > ./Documentation/devicetree/bindings/pci/pci.txt
> 
> Shawn:
> 
> 	This file should be removed. It is already merge to Rob's dt-scheme
> as PCIe standard properties.
> 
> See: https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/pci/pci-bus-common.yaml

Ah, thanks!

Rob,

So it's no longer the case that kernel Documentation/devicetree/bindings
has all bindings documentation?  Or it's never been the case?  I used to
grep a property in the folder to see if it's documented or not.

Shawn

Re: [PATCH v6 0/11] PCI: imx6: Add a method to handle CLKREQ# override

[Shawn Guo]

On Wed, Oct 15, 2025 at 11:04:17AM +0800, Richard Zhu wrote:
> [PATCH v6 01/11] arm64: dts: imx95-15x15-evk: Add supports-clkreq
> [PATCH v6 02/11] arm64: dts: imx95-19x19-evk: Add supports-clkreq
> [PATCH v6 03/11] arm64: dts: imx8mm-evk: Add supports-clkreq property
> [PATCH v6 04/11] arm64: dts: imx8mp-evk: Add supports-clkreq property
> [PATCH v6 05/11] arm64: dts: imx8mq-evk: Add supports-clkreq property
> [PATCH v6 06/11] arm64: dts: imx8qm-mek: Add supports-clkreq property
> [PATCH v6 07/11] arm64: dts: imx8qxp-mek: Add supports-clkreq

Applied these, thanks!

Re: [PATCH v6 01/11] arm64: dts: imx95-15x15-evk: Add supports-clkreq property to PCIe M.2 port

[Frank Li]

On Wed, Nov 12, 2025 at 09:50:43AM +0800, Shawn Guo wrote:
> On Tue, Nov 11, 2025 at 11:10:05AM -0500, Frank Li wrote:
> > On Tue, Nov 11, 2025 at 08:02:35AM +0000, Hongxing Zhu wrote:
> > > > -----Original Message-----
> > > > From: Shawn Guo <shawnguo2@yeah.net>
> > > > Sent: 2025年11月11日 15:11
> > > > To: Hongxing Zhu <hongxing.zhu@nxp.com>
> > > > Cc: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de;
> > > > lpieralisi@kernel.org; kwilczynski@kernel.org; mani@kernel.org;
> > > > robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org;
> > > > bhelgaas@google.com; shawnguo@kernel.org; s.hauer@pengutronix.de;
> > > > kernel@pengutronix.de; festevam@gmail.com; linux-pci@vger.kernel.org;
> > > > linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> > > > imx@lists.linux.dev; linux-kernel@vger.kernel.org
> > > > Subject: Re: [PATCH v6 01/11] arm64: dts: imx95-15x15-evk: Add
> > > > supports-clkreq property to PCIe M.2 port
> > > >
> > > > On Wed, Oct 15, 2025 at 11:04:18AM +0800, Richard Zhu wrote:
> > > > > According to PCIe r6.1, sec 5.5.1.
> > > > >
> > > > > The following rules define how the L1.1 and L1.2 substates are entered:
> > > > > Both the Upstream and Downstream Ports must monitor the logical state
> > > > > of the CLKREQ# signal.
> > > > >
> > > > > Typical implement is using open drain, which connect RC's clkreq# to
> > > > > EP's clkreq# together and pull up clkreq#.
> > > > >
> > > > > imx95-15x15-evk matches this requirement, so add supports-clkreq to
> > > > > allow PCIe device enter ASPM L1 Sub-State.
> > > > >
> > > > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > > > > ---
> > > > >  arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 1 +
> > > > >  1 file changed, 1 insertion(+)
> > > > >
> > > > > diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> > > > > b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> > > > > index 148243470dd4a..3ee032c154fa3 100644
> > > > > --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> > > > > +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> > > > > @@ -556,6 +556,7 @@ &pcie0 {
> > > > >  	pinctrl-names = "default";
> > > > >  	reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>;
> > > > >  	vpcie-supply = <&reg_m2_pwr>;
> > > > > +	supports-clkreq;
> > > >
> > > > Is binding updated for this property?
> > > >
> > > > Shawn
> > > >
> > > Hi Shawn:
> > > As I know that It's a documented binding property as below.
> > > - supports-clkreq:
> > >    If present this property specifies that CLKREQ signal routing exists from
> > >    root port to downstream device and host bridge drivers can do programming
> > >    which depends on CLKREQ signal existence. For example, programming root port
> > >    not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
> > > ./Documentation/devicetree/bindings/pci/pci.txt
> >
> > Shawn:
> >
> > 	This file should be removed. It is already merge to Rob's dt-scheme
> > as PCIe standard properties.
> >
> > See: https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/pci/pci-bus-common.yaml
>
> Ah, thanks!
>
> Rob,
>
> So it's no longer the case that kernel Documentation/devicetree/bindings
> has all bindings documentation?  Or it's never been the case?  I used to
> grep a property in the folder to see if it's documented or not.

Many common properties already moved to
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/

Just need run CHEKC_DTBS. Now imx6 (ARM) DTB warning should be around
1k line (after applied my other warning cleanup patches). If narrow down to
patch touched boards, only few warings.

imx8 (ARM64) should be below 100 lines, which cause by recently binding
doc change, suppose it should zero.

Frank

>
> Shawn
>