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Fri, 14 Nov 2025 12:34:19 -0800 (PST) Received: from geday ([2804:7f2:800b:9c95::dead:c001]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-bc36db22439sm5747058a12.4.2025.11.14.12.34.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Nov 2025 12:34:18 -0800 (PST) Date: Fri, 14 Nov 2025 17:34:05 -0300 From: Geraldo Nascimento To: Shawn Lin Cc: Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci , linux-arm-kernel , linux-kernel , devicetree , krzk+dt , conor+dt , Johan Jonker , linux-rockchip , Simon Glass , Philipp Tomsich , Kever Yang , Tom Rini , u-boot@lists.denx.de, =?utf-8?B?5byg54Oo?= Subject: Re: [PATCH] arm64: dts: rockchip: align bindings to PCIe spec Message-ID: References: <67b605b0-7046-448a-bc9b-d3ac56333809@rock-chips.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251114_123420_712788_0EF78F62 X-CRM114-Status: GOOD ( 17.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Nov 14, 2025 at 05:16:21PM +0800, Shawn Lin wrote: > Don't worry, it's helpful, so I think Ye could have a look. > May I ask if the failure only happened to one specific board? Hi Shawn, Yes, testing is restricted to my Radxa Rock Pi N10 board. > > Another thing I noticed is about one commit: > 114b06ee108c ("PCI: rockchip: Set Target Link Speed to 5.0 GT/s before > retraining") > > It said: "Rockchip controllers can support up to 5.0 GT/s link speed." > But we issued an errata long time ago to announced it doesn't, you could > also check the PCIe part of RK3399 datasheet: > https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf OK, I'm partly responsible for that as author of the commit in question. First off let me say I do not intend to send any patches setting max-link-speed to TWO for this platform. I understand you issued an erratum, but are you absolutely sure about that erratum? Because my testing shows otherwise: --- With max-link-speed = <2> pci 0000:01:00.0: 16.000 Gb/s available PCIe bandwidth, limited by 5.0 GT/s PCIe x4 link at 0000:00:00.0 (capable of 31.504 Gb/s with 8.0 GT/s PCIe x4 link) /dev/nvme0n1: Timing cached reads: 3002 MB in 2.00 seconds = 1502.21 MB/sec Timing buffered disk reads: 2044 MB in 3.00 seconds = 680.79 MB/sec --- With max-link-speed = <1> pci 0000:01:00.0: 8.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s PCIe x4 link at 0000:00:00.0 (capable of 31.504 Gb/s with 8.0 GT/s PCIe x4 link) /dev/nvme0n1: Timing cached reads: 2730 MB in 2.00 seconds = 1366.15 MB/sec Timing buffered disk reads: 2028 MB in 3.00 seconds = 675.71 MB/sec --- As you can see, not only the kernel PCI driver recognizes 5.0 GT/s PCIe link but there's even a marginal increase in cached reads as measured by hdparm, the gains are of course limited by CPU performance. > Also we set max-link-speed to ONE in rk3399-base.dtsi but seems another > patch slip in: 755fff528b1b ("arm64: dts: rockchip: add variables for > pcie completion to helios64") I can't speak for patches I haven't authored, but I believe you're welcome to send a correction. Thank you, Geraldo Nascimento