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Sat, 15 Nov 2025 01:51:36 -0800 (PST) Received: from geday ([2804:7f2:800b:a121::dead:c001]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2a49db102f5sm16211340eec.4.2025.11.15.01.51.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Nov 2025 01:51:35 -0800 (PST) Date: Sat, 15 Nov 2025 06:51:29 -0300 From: Geraldo Nascimento To: Dragan Simic Cc: linux-rockchip@lists.infradead.org, Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski , Conor Dooley , Johan Jonker Subject: Re: [PATCH 2/3] PCI: rockchip-host: comment danger of 5.0 GT/s speed Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251115_015137_241235_DA29262D X-CRM114-Status: GOOD ( 21.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Nov 15, 2025 at 10:30:49AM +0100, Dragan Simic wrote: > Hello Geraldo, > > On Saturday, November 15, 2025 10:10 CET, Geraldo Nascimento wrote: > > According to Rockchip sources, there is grave danger in enabling 5.0 > > GT/s speed for this core. Add a comment documenting that danger and > > discouraging end-users from forcing higher speed through DT changes. > > > > Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock-chips.com/ > > Reported-by: Shawn Lin > > Signed-off-by: Geraldo Nascimento > > --- > > drivers/pci/controller/pcie-rockchip-host.c | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c > > index ee1822ca01db..7e6ff76466b7 100644 > > --- a/drivers/pci/controller/pcie-rockchip-host.c > > +++ b/drivers/pci/controller/pcie-rockchip-host.c > > @@ -332,6 +332,11 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip) > > /* > > * Enable retrain for gen2. This should be configured only after > > * gen1 finished. > > + * > > + * According to Rockchip this path is dangerous and may lead to > > + * catastrophic failure. Even if the odds are small, users are > > + * still discouraged to engage the corresponding DT option. > > + * > > */ > > status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2); > > status &= ~PCI_EXP_LNKCTL2_TLS; > > Looking good to me, thanks for this patch! There's no need > to emit warnings here, because they'd be emitted already in > the rockchip_pcie_parse_dt() function. > > Please feel free to include > > Reviewed-by: Dragan Simic > I disagree, I think the comment stands. Even if we reduce to one line, ex: + May cause damage Regards, Geraldo Nascimento