From: Peter Chen <peter.chen@cixtech.com>
To: Jun Guo <jun.guo@cixtech.com>
Cc: <fugang.duan@cixtech.com>, <robh@kernel.org>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>, <broonie@kernel.org>,
<linux-spi@vger.kernel.org>, <michal.simek@amd.com>,
<cix-kernel-upstream@cixtech.com>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 3/3] arm64: dts: cix: add a compatible string for the cix sky1 SoC
Date: Mon, 17 Nov 2025 17:32:11 +0800 [thread overview]
Message-ID: <aRrrm5kEYGIG-aP_@nchen-desktop> (raw)
In-Reply-To: <20251031073003.3289573-4-jun.guo@cixtech.com>
On 25-10-31 15:30:03, Jun Guo wrote:
> The SPI IP design for the cix sky1 SoC uses a FIFO with a data width
> of 32 bits, instead of the default 8 bits. Therefore, a compatible
> string is added to specify the FIFO data width configuration for the
> cix sky1 SoC.
>
> Signed-off-by: Jun Guo <jun.guo@cixtech.com>
Applied, Thanks.
Peter
> ---
> arch/arm64/boot/dts/cix/sky1.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
> index d21387224e79..189b9a3be55c 100644
> --- a/arch/arm64/boot/dts/cix/sky1.dtsi
> +++ b/arch/arm64/boot/dts/cix/sky1.dtsi
> @@ -265,7 +265,7 @@ i2c7: i2c@4080000 {
> };
>
> spi0: spi@4090000 {
> - compatible = "cdns,spi-r1p6";
> + compatible = "cix,sky1-spi-r1p6", "cdns,spi-r1p6";
> reg = <0x0 0x04090000 0x0 0x10000>;
> clocks = <&scmi_clk CLK_TREE_FCH_SPI0_APB>,
> <&scmi_clk CLK_TREE_FCH_SPI0_APB>;
> @@ -275,7 +275,7 @@ spi0: spi@4090000 {
> };
>
> spi1: spi@40a0000 {
> - compatible = "cdns,spi-r1p6";
> + compatible = "cix,sky1-spi-r1p6", "cdns,spi-r1p6";
> reg = <0x0 0x040a0000 0x0 0x10000>;
> clocks = <&scmi_clk CLK_TREE_FCH_SPI1_APB>,
> <&scmi_clk CLK_TREE_FCH_SPI1_APB>;
> --
> 2.34.1
>
--
Best regards,
Peter
next prev parent reply other threads:[~2025-11-17 9:32 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-31 7:30 [PATCH v3 0/3] spi-cadence: support transmission with bits_per_word of 16 and 32 Jun Guo
2025-10-31 7:30 ` [PATCH v3 1/3] dt-bindings: spi: spi-cadence: update DT binding docs to support cix sky1 SoC Jun Guo
2025-10-31 15:10 ` Conor Dooley
2025-10-31 7:30 ` [PATCH v3 2/3] spi: spi-cadence: supports transmission with bits_per_word of 16 and 32 Jun Guo
2025-10-31 7:30 ` [PATCH v3 3/3] arm64: dts: cix: add a compatible string for the cix sky1 SoC Jun Guo
2025-11-17 9:32 ` Peter Chen [this message]
2025-11-14 17:07 ` (subset) [PATCH v3 0/3] spi-cadence: support transmission with bits_per_word of 16 and 32 Mark Brown
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