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Mon, 17 Nov 2025 17:42:13 -0800 Date: Mon, 17 Nov 2025 17:42:12 -0800 From: Nicolin Chen To: "Tian, Kevin" CC: "joro@8bytes.org" , "afael@kernel.org" , "bhelgaas@google.com" , "alex@shazbot.org" , "jgg@nvidia.com" , "will@kernel.org" , "robin.murphy@arm.com" , "lenb@kernel.org" , "baolu.lu@linux.intel.com" , "linux-arm-kernel@lists.infradead.org" , "iommu@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "linux-acpi@vger.kernel.org" , "linux-pci@vger.kernel.org" , "kvm@vger.kernel.org" , "patches@lists.linux.dev" , "Jaroszynski, Piotr" , "Sethi, Vikram" , "helgaas@kernel.org" , "etzhao1900@gmail.com" Subject: Re: [PATCH v5 5/5] pci: Suspend iommu function prior to resetting a device Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0002992A:EE_|DM6PR12MB4139:EE_ X-MS-Office365-Filtering-Correlation-Id: 39a778ae-a752-434a-8c63-08de2643bd50 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|7416014|376014; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2025 01:42:31.2162 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 39a778ae-a752-434a-8c63-08de2643bd50 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4139 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251117_174241_375109_40D838B2 X-CRM114-Status: GOOD ( 28.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Nov 18, 2025 at 12:29:43AM +0000, Tian, Kevin wrote: > > From: Nicolin Chen > > Sent: Tuesday, November 18, 2025 3:27 AM > > > > On Mon, Nov 17, 2025 at 04:52:05AM +0000, Tian, Kevin wrote: > > > > From: Nicolin Chen > > > > Sent: Saturday, November 15, 2025 2:01 AM > > > > > > > > On Fri, Nov 14, 2025 at 09:45:31AM +0000, Tian, Kevin wrote: > > > > > > From: Nicolin Chen > > > > > > Sent: Tuesday, November 11, 2025 1:13 PM > > > > > > > > > > > > +/* > > > > > > + * Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software > > disables > > > > ATS > > > > > > before > > > > > > + * initiating a reset. Notify the iommu driver that enabled ATS. > > > > > > + */ > > > > > > +int pci_reset_iommu_prepare(struct pci_dev *dev) > > > > > > +{ > > > > > > + if (pci_ats_supported(dev)) > > > > > > + return iommu_dev_reset_prepare(&dev->dev); > > > > > > + return 0; > > > > > > +} > > > > > > > > > > the comment says "driver that enabled ATS", but the code checks > > > > > whether ATS is supported. > > > > > > > > > > which one is desired? > > > > > > > > The comments says "the iommu driver that enabled ATS". It doesn't > > > > conflict with what the PCI core checks here? > > > > > > actually this is sent to all IOMMU drivers. there is no check on whether > > > a specific driver has enabled ATS in this path. > > > > But the comment doesn't say "check".. > > > > How about "Notify the iommu driver that enables/disables ATS"? > > > > The point is that pci_enable_ats() is called in iommu drivers. > > > > but in current way even an iommu driver which doesn't call > pci_enable_ats() will also be notified then I didn't see the > point of adding an attribute to "the iommu driver". Hmm, that's a fair point. Having looked closely, I see only AMD and ARM call that to enable ATs. How others (e.g. Intel) enable it? And how do you think of the followings? /* * Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software disables ATS before * initiating a reset. Though not all IOMMU drivers calls pci_enable_ats(), it * only gets invoked in IOMMU driver. And it is racy to check dev->ats_enabled * here, as a concurrent IOMMU attachment can enable ATS right after this line. * * Notify the IOMMU driver to stop IOMMU translations until the reset is done, * to ensure that the ATS function and its related invalidations are disabled. */ Thanks Nicolin