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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?RNE29PwFOBxpQqG+WZfxE/iaaTS6sF/iic0CW7cFerkzIngQCFedFuEAxBxv?= =?us-ascii?Q?o0OefUqcbowPlbtT0KNnSAqBwU/lm2cTpy6nPVEXfO3rOaBqMZ92vzlE/Kf7?= =?us-ascii?Q?dLufqh5A4itGIhjkYct39udOfiXO9w4RhyMznyRUVg3DiDv/les7/RyPBKz5?= =?us-ascii?Q?6V1qYj7bz/H/ntngo8GYUiA5qldegRtC1rywHomzScv3J/d6M3CjNxOKUbu8?= =?us-ascii?Q?Zlggrns531YeZrxcGZtWEnX8P274wLrbe/XauQfiGh1IQhlVxmG+fZt0Qoki?= =?us-ascii?Q?4sfbfH+h1KjUSvdJJ+MxZucAP4xistSTkIdOGxx7iiPJlAWsE5Od1scFpFsI?= =?us-ascii?Q?ZC4w08cjeny+llJBQppuU/gH5T9eIG/VaKejqYisMY/0e5T1YPo+swBjxM1U?= =?us-ascii?Q?kbWOfrX7BDn2Fq5wfC/jVzh2zi56QgVsgP1x+6cbM8Ue/lmk6EALZAqB1jDR?= =?us-ascii?Q?GdjO6DPracDd+iBdz8otacVTzjhBoBi8upMZj1wKw8XEUuCo1f/UHZTkTETJ?= =?us-ascii?Q?Vw2Ja7hfP7GeMaSVnXRXVJnQta9BV6uIr6IhBRMT72TCt+oQlfsDiY95jeT7?= =?us-ascii?Q?4vDxa/QYDuEyWyBsDxokmezh/4egC5MPBnKa0QfrvFU7qdFowlsO+Qo5m+ZU?= =?us-ascii?Q?h5IlbKyC12W9IsIwTUhHGkWWB6GrfdAx3OM3ln9BlzBlzJWQP68k2AnbhtvG?= =?us-ascii?Q?CwnsvGBV5cSSQNHzremjlDu49GHbl5moneIPjiutZ6Tjw2dqGLLMlJs4NCz2?= =?us-ascii?Q?JCD2Tw/uHbrurFcEnpmMVhhBAbbCmgh6UI0Lslws7Ld45JlPpS1IcxezASVg?= =?us-ascii?Q?S8n6BIXLB0/Si3zhJkYgzIfqQjpMCip2/nrG57VuGGntZtCAOwyIc/bbGDHr?= =?us-ascii?Q?B6pMDXFcchgrRKbpU2w9j/2wfX91F+WgTA2Gu4zBTv4F8u0xS+xCxY1pctZd?= =?us-ascii?Q?xYDbTMmNk3q8Jd6izCFV2MEcj4HUOTg9VnQq8R/Vg6z5pVq58+/ZMavkxKEp?= =?us-ascii?Q?Bafjt+16cvuyHvFtUTimymbrohiO+B2nTF1Dmh+f0HGiJetWVMt0ZykQtfu2?= =?us-ascii?Q?Md9BfGXcO+N73v1Bq14fRk3QhG8zw8W1CA2WaJQh8x4Mnh852SY5Phe/5vrs?= =?us-ascii?Q?EiLPZPPhemZMJRmMGpRWFBO22+HkzM/hMCQo27Tmapoicrli9XTSq8/NH8WQ?= =?us-ascii?Q?MfYK4vgBf/zA1Jm1WNAAMH4nuNT/jWkRS3BNPReq2MlvZgeZqCziqBoTF5b+?= =?us-ascii?Q?nWR9QukwiuChTGu7bCcl31++pc15HiX5s2vlPMvBccoyrRTJu6+tmey+rgYf?= =?us-ascii?Q?6BR2NiVhv/4N8JsbokDKq8sgQviRCilX9MKGZUvo/iyJd3+34p9pvupnzM7y?= =?us-ascii?Q?MxUgE6kC9r5EmmmL8RrTp3A6X7JT3kPUUp1MPW6+MKsbqGymnL8DNX4cuzX0?= =?us-ascii?Q?ggcEv1bBDp6/Yqj4jIv9ZjwifDxSnEMLGasqvHk7Q2qmX846Gcja1b0G8w0+?= =?us-ascii?Q?WcnSJ5wB33d/Y7nASI2DlsrdDKrdFBeg8uOVNd2vjPuT3OGMfPv4BmM9SaGV?= =?us-ascii?Q?7TZZ8q72e2/COJ5ofnvmOEvWGoE7XgOslG4HlsC7?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 29c56e94-3846-4a93-2a6f-08de26f2a35b X-MS-Exchange-CrossTenant-AuthSource: DB9PR04MB9626.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2025 22:34:30.0009 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: oyHoK/BBzCDDdOb1xdkB48oOI/1gh3Y++JgE2B4Vs0iIhwQsJV9DDyQuXV79t5srz5v5MpsW81IRx6vVWnAn/A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB9332 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251118_143436_923776_B843BCE0 X-CRM114-Status: GOOD ( 29.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Nov 18, 2025 at 03:42:15PM -0600, Bjorn Helgaas wrote: > From: Bjorn Helgaas > > L1 PM Substates require the CLKREQ# signal and may also require > device-specific support. If CLKREQ# is not supported or driver support is > lacking, enabling L1.1 or L1.2 may cause errors when accessing devices, > e.g., > > nvme nvme0: controller is down; will reset: CSTS=0xffffffff, PCI_STATUS=0x10 > > If the kernel is built with CONFIG_PCIEASPM_POWER_SUPERSAVE=y or users > enable L1.x via sysfs, users may trip over these errors even if L1 > Substates haven't been enabled by firmware or the driver. > > To prevent such errors, disable advertising the L1 PM Substates unless the > driver sets "dw_pcie.l1ss_support" to indicate that it knows CLKREQ# is > present and any device-specific configuration has been done. > > Set "dw_pcie.l1ss_support" in tegra194 (if DT includes the > "supports-clkreq' property) and qcom (for cfg_2_7_0, cfg_1_9_0, cfg_1_34_0, > and cfg_sc8280xp controllers) so they can continue to use L1 Substates. > > Based on Niklas's patch: > https://patch.msgid.link/20251017163252.598812-2-cassel@kernel.org > > Signed-off-by: Bjorn Helgaas > --- > .../pci/controller/dwc/pcie-designware-ep.c | 2 ++ > .../pci/controller/dwc/pcie-designware-host.c | 2 ++ > drivers/pci/controller/dwc/pcie-designware.c | 24 +++++++++++++++++++ > drivers/pci/controller/dwc/pcie-designware.h | 2 ++ > drivers/pci/controller/dwc/pcie-qcom.c | 2 ++ > drivers/pci/controller/dwc/pcie-tegra194.c | 3 +++ > 6 files changed, 35 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c > index 7f2112c2fb21..ad6c0fd67a65 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > @@ -966,6 +966,8 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) > if (ep->ops->init) > ep->ops->init(ep); > > + dw_pcie_hide_unsupported_l1ss(pci); > + And, I don't think EP need clean L1SS CAP flags. If EP don't support L1SS, it should be force pull down #clkreq. EP don't know if #clkreq connected in host boards, assume EP with same software, which can run at two difference host system, one host system connect #clkreq, the other system have not connect #clkreq. otherwords, support-clkreq property should be only for RC side. not EP side. EP side l1ss support should depend on specific epf function and controller's capablity. Frank > ptm_cap_base = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM); > > /* > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 20c9333bcb1c..7abeb771e32d 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -1060,6 +1060,8 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) > PCI_COMMAND_MASTER | PCI_COMMAND_SERR; > dw_pcie_writel_dbi(pci, PCI_COMMAND, val); > > + dw_pcie_hide_unsupported_l1ss(pci); > + > dw_pcie_config_presets(pp); > /* > * If the platform provides its own child bus config accesses, it means > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index c644216995f6..6e6a0dac5b53 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -1081,6 +1081,30 @@ void dw_pcie_edma_remove(struct dw_pcie *pci) > dw_edma_remove(&pci->edma); > } > > +void dw_pcie_hide_unsupported_l1ss(struct dw_pcie *pci) > +{ > + u16 l1ss; > + u32 l1ss_cap; > + > + if (pci->l1ss_support) > + return; > + > + l1ss = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); > + if (!l1ss) > + return; > + > + /* > + * Unless the driver claims "l1ss_support", don't advertise L1 PM > + * Substates because they require CLKREQ# and possibly other > + * device-specific configuration. > + */ > + l1ss_cap = dw_pcie_readl_dbi(pci, l1ss + PCI_L1SS_CAP); > + l1ss_cap &= ~(PCI_L1SS_CAP_PCIPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_1 | > + PCI_L1SS_CAP_PCIPM_L1_2 | PCI_L1SS_CAP_ASPM_L1_2 | > + PCI_L1SS_CAP_L1_PM_SS); > + dw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, l1ss_cap); > +} > + > void dw_pcie_setup(struct dw_pcie *pci) > { > u32 val; > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index e995f692a1ec..a68eea47d451 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -516,6 +516,7 @@ struct dw_pcie { > int max_link_speed; > u8 n_fts[2]; > struct dw_edma_chip edma; > + bool l1ss_support; /* L1 PM Substates support */ > struct clk_bulk_data app_clks[DW_PCIE_NUM_APP_CLKS]; > struct clk_bulk_data core_clks[DW_PCIE_NUM_CORE_CLKS]; > struct reset_control_bulk_data app_rsts[DW_PCIE_NUM_APP_RSTS]; > @@ -573,6 +574,7 @@ int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, > int type, u64 parent_bus_addr, > u8 bar, size_t size); > void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index); > +void dw_pcie_hide_unsupported_l1ss(struct dw_pcie *pci); > void dw_pcie_setup(struct dw_pcie *pci); > void dw_pcie_iatu_detect(struct dw_pcie *pci); > int dw_pcie_edma_detect(struct dw_pcie *pci); > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 805edbbfe7eb..61c2f4e2f74d 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1067,6 +1067,8 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) > val &= ~REQ_NOT_ENTR_L1; > writel(val, pcie->parf + PARF_PM_CTRL); > > + pci->l1ss_support = true; > + > val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); > val |= EN; > writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c > index 10e74458e667..3934757baa30 100644 > --- a/drivers/pci/controller/dwc/pcie-tegra194.c > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c > @@ -703,6 +703,9 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie) > val |= (pcie->aspm_pwr_on_t << 19); > dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val); > > + if (pcie->supports_clkreq) > + pci->l1ss_support = true; > + > /* Program L0s and L1 entrance latencies */ > val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); > val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK; > -- > 2.43.0 >