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From: Sunil V L <sunilvl@ventanamicro.com>
To: niliqiang <ni_liqiang@126.com>
Cc: apatel@ventanamicro.com, ajones@ventanamicro.com,
	anup@brainfault.org, atishp@atishpatra.org, bjorn@kernel.org,
	conor+dt@kernel.org, devicetree@vger.kernel.org,
	frowand.list@gmail.com, krzysztof.kozlowski+dt@linaro.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	maz@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com,
	robh+dt@kernel.org, saravanak@google.com, tglx@linutronix.de,
	hu.yuye@zte.com.cn, deng.weixian@zte.com.cn,
	ni.liqiang@zte.com.cn
Subject: Re: [PATCH v16 6/9] irqchip: Add RISC-V advanced PLIC driver for direct-mode
Date: Fri, 21 Nov 2025 14:20:56 +0530	[thread overview]
Message-ID: <aSAn8DdQVBBzenlJ@sunil-laptop> (raw)
In-Reply-To: <20251120144311.5083-1-ni_liqiang@126.com>

Hi Liqiang,

On Thu, Nov 20, 2025 at 10:43:11PM +0800, niliqiang wrote:
> > diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-riscv-aplic-main.c
> > +static const struct of_device_id aplic_match[] = {
> > + { .compatible = "riscv,aplic" },
> > + {}
> > +};
> > +
> > +static struct platform_driver aplic_driver = {
> > + .driver = {
> > +  .name  = "riscv-aplic",
> > +  .of_match_table = aplic_match,
> > + },
> > + .probe = aplic_probe,
> > +};
> > +builtin_platform_driver(aplic_driver);
> 
> Dear Anup Patel and all concerned,
> 
> I am writing to inquire about the historical rationale behind defining the APLIC driver's
> initialization priority using builtin_platform_driver in the current implementation.
> 
> In our environment, we are encountering an issue where this priority level causes ACPI-based PCIe
> enumeration to be executed in the system_unbound_wq work queue. This parallel execution model
> results in PCIe devices being enumerated in an arbitrary order rather than strictly following the
> sequence defined in the ACPI DSDT table.
> 
> The random enumeration order is adversely affecting customer experience, particularly in scenarios
> where device ordering is critical for proper system operation or application compatibility.
> 
> We are considering modifying the APLIC driver's initialization priority to ensure PCIe enumeration
> occurs sequentially according to the DSDT specification. However, before proceeding with such
> changes, we wanted to consult with you regarding:
> 
> 1. Were there specific technical considerations that led to the current priority selection?
> 2. Are there any potential side effects or broader impacts that we might have overlooked?
> 3. Would you support such a priority adjustment, or do you have alternative suggestions to 
> address the enumeration order issue?
> 
> We greatly appreciate your insights and expertise on this matter, as it will help us make an
> informed decision while maintaining system stability and compatibility.
> 
> Thank you for your time and consideration.
> 

IRQ subsystem maintainers rejected the idea of relying on initcalls to
enforce probe order because initcalls do not guarantee ordering. The
Linux driver model instead ensures probe order through device
dependencies. Since PCI INTx depends on the APLIC being probed first,
the PCI host bridge probe cannot occur until after the APLIC probe
completes. This requirement and behavior are the same for both DT and
ACPI. In DT, the driver model uses fw_devlink to establish probe
ordering, while in ACPI this is handled through either an explicit _DEP
or, on RISC-V, the GSI mapping.

Typically, this dependency appears in the DSDT only for the PCI host
bridge. Individual PCIe devices are enumerated through the standard PCI
scan once the host bridge has been probed. Therefore, I’m not sure what
you meant by a probe sequence defined in the DSDT for PCIe devices.

Regards,
Sunil


  reply	other threads:[~2025-11-21  8:51 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-07 14:02 [PATCH v16 0/9] Linux RISC-V AIA Support Anup Patel
2024-03-07 14:02 ` [PATCH v16 1/9] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2024-03-07 14:03 ` [PATCH v16 2/9] irqchip: Add RISC-V incoming MSI controller early driver Anup Patel
2024-04-19  3:23   ` Eric Cheng
2024-04-19  3:44     ` Anup Patel
2024-04-19  3:55       ` Eric Cheng
2024-03-07 14:03 ` [PATCH v16 3/9] irqchip/riscv-imsic: Add device MSI domain support for platform devices Anup Patel
2024-03-07 14:03 ` [PATCH v16 4/9] irqchip/riscv-imsic: Add device MSI domain support for PCI devices Anup Patel
2024-03-07 14:03 ` [PATCH v16 5/9] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2024-03-07 14:03 ` [PATCH v16 6/9] irqchip: Add RISC-V advanced PLIC driver for direct-mode Anup Patel
2025-11-20 14:43   ` niliqiang
2025-11-21  8:50     ` Sunil V L [this message]
2025-11-21 13:54       ` niliqiang
2025-11-22  9:37         ` Marc Zyngier
2025-11-25 16:07           ` niliqiang
2025-11-25 16:42             ` Thomas Gleixner
2025-11-26 16:15               ` niliqiang
2024-03-07 14:03 ` [PATCH v16 7/9] irqchip/riscv-aplic: Add support for MSI-mode Anup Patel
2024-03-07 14:03 ` [PATCH v16 8/9] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2024-03-07 14:03 ` [PATCH v16 9/9] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
2024-03-07 14:11 ` [PATCH v16 0/9] Linux RISC-V AIA Support Anup Patel
2024-03-07 21:03   ` Thomas Gleixner
2024-03-08 11:11 ` Björn Töpel
2024-03-08 11:13   ` Björn Töpel

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