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Mon, 24 Nov 2025 23:43:12 -0800 Date: Mon, 24 Nov 2025 23:43:11 -0800 From: Nicolin Chen To: Jason Gunthorpe CC: Will Deacon , , , , , , , , , , , Subject: Re: [PATCH v5 4/7] iommu/arm-smmu-v3: Pre-allocate a per-master invalidation array Message-ID: References: <20251124230845.GN153257@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E7:EE_|MN2PR12MB4189:EE_ X-MS-Office365-Filtering-Correlation-Id: decdc4fa-1e97-4c1d-4f69-08de2bf64dd3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?D2ZVd/H55CHcaGKRPHHJ3nuKodj9EuVpBMxT0vSy//GMw2GDdg2ryDEzWm9q?= =?us-ascii?Q?z8NFrFhhBBaNkNM/o5ay8DpeTlDisKUCQSo+9cOTiou53b6yqQRjQD8JgfiK?= =?us-ascii?Q?aKZSHUuQR3uZtRQ/4EOIRfkOwzAnBfwiClH+Fh1vW18VEH8CHw3FjBQv9vXA?= =?us-ascii?Q?ZPM45ixjbwHoqlKorRIj1OSZ07Y4Us27OiXrWbdxYU5h9Qtvgkn8PYylxgwK?= =?us-ascii?Q?zF92MNjFbeom3XgIwuMb4Ni1/MUnXMBVs3FuaM0HSz/pDfcwqaopeJVupZOm?= =?us-ascii?Q?8HoCTCzh/k4Z5QBMnEfdPlGdNnYXVoLOot9Tp9T65REuu3t1r32pfFPEDOmm?= =?us-ascii?Q?rsWEo33NsfJsyCxA0TawM8Qu1hsfR0zF59YoO3iwYyX9WNrYBghJ5bufiXVf?= =?us-ascii?Q?eVkweFBQ52HSj14CnUjmoChhSn2nEYEhWBIAqNqIcm38WSoq0IBuLzlQfPrJ?= =?us-ascii?Q?9P9Y2xaPhlkDDgtA/nDx7t9BpNEHLJ44X9uYix0apHg1L7RygIXaOflzpHWm?= =?us-ascii?Q?s+BGF6067iUQtkEx7wCXNGJBQO6Vw6WI4HHwtHyNRSCXAek8h7I733kYAEbD?= =?us-ascii?Q?NjhKWhZBqw/GykhyepO6f2oXUTBlbSkJZT2QEduffjAQB/DYELh4ooeZRAuc?= =?us-ascii?Q?pQW6+Ry8+v8RaepGacbzDLevCTwSYfhGZ8eagzeWwbPIuSRF6u3fz3tBLfQy?= =?us-ascii?Q?ICmwBkMyJbe4aOEvQYgWJz43Ch5shmRMCTJuRTFRLGOFv6Sy98dKsHpifTJ+?= =?us-ascii?Q?Xa93QqLMTTsZ9P0X5l+jw62hmQwilpK0AMidx+my8bpiW4DDsHMJKLRqyRLg?= =?us-ascii?Q?H8Fk1ZV99bXYSLUo89P6nlL+Jjlc1w+CqXxNxdWQr/AYw1+2BnaCbPzs0KuK?= =?us-ascii?Q?F9jdQSu2uNAmH82gM5jlnPsZUcjRE8d5TpdJIJoFxvg+APQnfdCcTJSDZCwP?= =?us-ascii?Q?1ilatzL+ZewDCzuwPyPNn+adZFhoGzKcYn2Y8gvVDNgowrg9MoRgjQ43Z5D7?= =?us-ascii?Q?dwWMKEAKicg0IZd1BqAbzMjEGzxAip95Ja3hF5TBxwR3ugX3JL+mwHIBToSk?= =?us-ascii?Q?ft077aFH42e3CrA/Pm/GXhjQVVpT+I29qoonDvEjs5sDjKW+qSFIeeoNAfj9?= =?us-ascii?Q?lnHM6u/LOu2DqSuIAfs1zoQQUhQwB1KqMG5yrYHnLifsoo/YmpNa1v5qx5vT?= =?us-ascii?Q?0zyzXsHneRY6CykT0ScES9fQ2tyGLecRMPuPhfE4RYUnD5A0xa0dXxE/EAhy?= =?us-ascii?Q?lKicaVfs66VJ2qfbmtVy3nUMW7SJKd3AIvJHaN38eiiz5N168JpcMZ+mpy1Q?= =?us-ascii?Q?h6t11TlIRdu1JtBzg3e5vmhC9JGnSRSAhnvyIlGlUK319b/2IBzFQ4JHNF+3?= =?us-ascii?Q?QtIK6nJLpD2jq93GXErWiQAj/jtSQeEmNZ/5gQRoPEqDjgMEHRfmMyhoWaGp?= =?us-ascii?Q?qOlFVM2MPUxp1Ub8lP4vAdd0dh4aXcG56+odZIwo2d/DYHCICgNkquHhhlkY?= =?us-ascii?Q?hw2ZLL53leZtLfQ9xt4Kqxo+353Jw7IylEXlDzNC/dGZ8oN/9ibdNd+gjeQy?= =?us-ascii?Q?O1ViqfSckArCwPlZPS0=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Nov 2025 07:43:19.9946 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: decdc4fa-1e97-4c1d-4f69-08de2bf64dd3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4189 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251124_234327_177052_609D8368 X-CRM114-Status: GOOD ( 33.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Nov 24, 2025 at 03:31:17PM -0800, Nicolin Chen wrote: > On Mon, Nov 24, 2025 at 07:08:45PM -0400, Jason Gunthorpe wrote: > > On Mon, Nov 24, 2025 at 02:43:58PM -0800, Nicolin Chen wrote: > > > On Mon, Nov 24, 2025 at 09:42:55PM +0000, Will Deacon wrote: > > > > On Sat, Nov 08, 2025 at 12:08:05AM -0800, Nicolin Chen wrote: > > > > > + /* Put the ids into order for sorted to_merge/to_unref arrays */ > > > > > + sort_nonatomic(fwspec->ids, fwspec->num_ids, > > > > > + sizeof(fwspec->ids[0]), arm_smmu_ids_cmp, NULL); > > > > > + /* ATS case adds num_ids of entries, on top of the base case */ > > > > > + master->build_invs = arm_smmu_invs_alloc(2 + fwspec->num_ids); > > > > > > > > Although I can't point at a specific issue here, I'm nervous about mutating > > > > the 'fwspec->ids' array from within the driver, The array isn't allocated > > > > or populated directly by the driver and so I don't think we really have any > > > > business sorting it. Could we hack iommu_fwspec_add_ids() to keep the array > > > > ordered instead? > > > > > > Yea, I think it makes sense to do it in the core, once we have the > > > data structure provided by the core as well. > > > > I would be more worried about sorting it everywhere for every > > driver. I feel confident SMMUv3 doesn't use it, but something really > > old and embedded focused like tegra or omap, IDK. > > > > So I wouldn't propose to change iommu_fwspec_add_ids(). > > Perhaps a different helper iommu_fwspec_add_ids_sorted()? Drivers > can choose to use the sorted version, when they want to implement > the invalidation array. And SMMU can be the first only caller. > > > If you want to be conservative then the thing to do is sort the > > master->streams that arm_smmu_insert_master() copies the fwspec > > into. It just has to be sorted prior to feeding it into the rbtree. > > > > Then consistently use master->streams as the sorted list. > > How about kmemdup() an local id array to bridge betwen fwspec->ids > and rbtree? Does this look okay? @@ -3713,6 +3713,7 @@ static int arm_smmu_insert_master(struct arm_smmu_device *smmu, { int i; int ret = 0; + u32 *ids, *ids_sorted = NULL; struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(master->dev); bool ats_supported = dev_is_pci(master->dev) && pci_ats_supported(to_pci_dev(master->dev)); @@ -3723,26 +3724,38 @@ static int arm_smmu_insert_master(struct arm_smmu_device *smmu, return -ENOMEM; master->num_streams = fwspec->num_ids; + ids = fwspec->ids; if (!ats_supported) { /* Base case has 1 ASID entry or maximum 2 VMID entries */ master->build_invs = arm_smmu_invs_alloc(2); } else { /* Put the ids into order for sorted to_merge/to_unref arrays */ - sort_nonatomic(fwspec->ids, fwspec->num_ids, - sizeof(fwspec->ids[0]), arm_smmu_ids_cmp, NULL); + if (fwspec->num_ids > 1) { + ids = kmemdup_array(fwspec->ids, fwspec->num_ids, + sizeof(*ids), GFP_KERNEL); + if (!ids) { + kfree(master->streams); + return -ENOMEM; + } + + sort_nonatomic(ids, fwspec->num_ids, sizeof(*ids), + arm_smmu_ids_cmp, NULL); + ids_sorted = ids; + } /* ATS case adds num_ids of entries, on top of the base case */ master->build_invs = arm_smmu_invs_alloc(2 + fwspec->num_ids); } - if (IS_ERR(master->build_invs)) { + if (!master->build_invs) { kfree(master->streams); - return PTR_ERR(master->build_invs); + ret = -ENOMEM; + goto out; } mutex_lock(&smmu->streams_mutex); for (i = 0; i < fwspec->num_ids; i++) { struct arm_smmu_stream *new_stream = &master->streams[i]; struct rb_node *existing; - u32 sid = fwspec->ids[i]; + u32 sid = ids[i]; new_stream->id = sid; new_stream->master = master; @@ -3779,6 +3792,8 @@ static int arm_smmu_insert_master(struct arm_smmu_device *smmu, } mutex_unlock(&smmu->streams_mutex); +out: + kfree(ids_sorted); return ret; } Thanks Nicolin