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Tue, 25 Nov 2025 16:56:43 -0800 Date: Tue, 25 Nov 2025 16:56:42 -0800 From: Nicolin Chen To: Jason Gunthorpe CC: Will Deacon , , , , , , , , , , , Subject: Re: [PATCH v5 5/7] iommu/arm-smmu-v3: Populate smmu_domain->invs when attaching masters Message-ID: References: <20251124231341.GO153257@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20251124231341.GO153257@nvidia.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD9:EE_|DS0PR12MB8042:EE_ X-MS-Office365-Filtering-Correlation-Id: f3883b56-68f9-44c8-0d9d-08de2c86b466 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Y8+XLWgFKX1qWHn7VroElFXpgdu05RvHBoKoFU5ZN7fy6793YZXnFa4UgwOj?= =?us-ascii?Q?AYiWV6aqhhfO6l3KnnNjg59G5bODbYzKIG4moEbSexjtpxODexZAE5SPfcs9?= =?us-ascii?Q?yDWLWB3QLz3nQwbZteCtcm0r0Rw1cqXzUK6ru5E0eJvHdXjG3JoG0kRIdWVI?= =?us-ascii?Q?tRy0VhmMCbr6zDAD41SBha6hSbHBJIroEsxMKVa1wQGh46CgNO6bVpEGrk8n?= =?us-ascii?Q?GfFG+qjRCXMVKWAXjo7Wv+Lu/S4LXEXYjOpyY91Zr9TnwKev4qzZRNOBseSf?= =?us-ascii?Q?K8sZl/1do3RtfzGaV08XDddjtjIKWQvMyBVNlEZvKNClEvSnZfH53HWVabzs?= =?us-ascii?Q?pQPziPVwRoJuCLrFl5NtPifKWcO7DGLWVwip/pTg3SkRDQ9LKNvT4dprKvcv?= =?us-ascii?Q?RQy82C9L/QZ2iwTKlXkFtBoSN5061OWJIsCA8Mdw9FJE+Ynm7CHyDF9kzscN?= =?us-ascii?Q?T2unCSv9LcUYLZwS+XZ/dKWr+vLfhAzRmzdBAkPGYFANzvYiz6gx++kUEoYK?= =?us-ascii?Q?7tEQJungR3tGtciYSsD/fOaduT/GQ3JezCzok8mit6JGbO7eNTsrbrb8Vivh?= =?us-ascii?Q?5QAIZNFUlQPXwIX1egk0eKpdVdQh+TqtpMUQTAsmpLak+o6Mu30LJ9siJTdG?= =?us-ascii?Q?MMup2J+EV61ADSqDJ6v1n4wzq1Bc7LakyYxcbLb2PCPaqLdPKrny77+IGoiG?= =?us-ascii?Q?iaZM4l/U4vfX3137sWWlE3Slv4uLr0K4pU5H2Bn/h6py0IqK+g6Tk8z5TsMY?= =?us-ascii?Q?US7hhHZA+9Kk8j002GLBsdEZ2KUDJYLR4q6DBRe/65IUqQUy/cSBjEAzptfc?= =?us-ascii?Q?VGB3xCa6Askbet+JNPacgn/tAjtw4N1uBcwzxTba7B/+0YET8UWy3wvOYtk1?= =?us-ascii?Q?BHoQvM0ewy3KFpkkHSIGF2tVP7y2pPScPqcB4oL2b1SdcGbkc+kkyi5lDmHB?= =?us-ascii?Q?3ZIQgJOfl6Org4DMqTtjmakqdbL1cxi84fNI5RXWNcdviDZRPebsMTdPPCXx?= =?us-ascii?Q?EcSisZ3Skjcx2AkluUVex/W5Qzq5mzsFfw1t3g7doa5sXC9ys373NYsqSE0K?= =?us-ascii?Q?+OQ+ixeePzP2K5YivW/It+1NMqztBs56bOrdpU6rH3Y8+oQpLNDQw6SULecZ?= =?us-ascii?Q?YM9Sy19S79QgWEmfdNQUPLIsOiiO/2hwnM1I+3acrlqXPRz4DG+zTjhB6RY7?= =?us-ascii?Q?Z45iDmIMYR2oKyLlJf4doXEdTM6n+uDqdUVDkHBGJnaH44gcGQGqZAhSYRvC?= =?us-ascii?Q?b4nMrF+L/ccX7bvRRH8/PhfkOBiAvcfd+qMX4HjAVe3P0LiBTnCTdgtAxBg3?= =?us-ascii?Q?rWvfi0gnt8+ORFm5vSP2eEYqUPswyiOFrj2mqWfq8QoVpyHl69pcoBnPX5Cy?= =?us-ascii?Q?o/p17R1ZKs4qOBscvohUUv590Bk9g+v2+ml8rNqvOetFkeaTMzDnv8oM4S5J?= =?us-ascii?Q?t6E8vnHS/0ytOdxdkommonojGhXmEgf2VW/id13kB3DyDQIFZ+kSPMH8K+78?= =?us-ascii?Q?X9FL7zQb3fOY2prQ/hJg2h5m0PMKoMuQtOxd6aE1PIz7hFcVv9D0MTzY2cRm?= =?us-ascii?Q?U/uKHbhs8hvvrHtQmRM=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2025 00:56:59.5170 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f3883b56-68f9-44c8-0d9d-08de2c86b466 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8042 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251125_165710_112186_37E6E2CA X-CRM114-Status: GOOD ( 26.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Nov 24, 2025 at 07:13:41PM -0400, Jason Gunthorpe wrote: > On Mon, Nov 24, 2025 at 09:43:18PM +0000, Will Deacon wrote: > > > + switch (smmu_domain->stage) { > > > + case ARM_SMMU_DOMAIN_SVA: > > > + case ARM_SMMU_DOMAIN_S1: > > > + *cur = (struct arm_smmu_inv){ > > > + .smmu = master->smmu, > > > + .type = INV_TYPE_S1_ASID, > > > + .id = smmu_domain->cd.asid, > > > + .size_opcode = e2h ? CMDQ_OP_TLBI_EL2_VA : > > > + CMDQ_OP_TLBI_NH_VA, > > > + .nsize_opcode = e2h ? CMDQ_OP_TLBI_EL2_ASID : > > > + CMDQ_OP_TLBI_NH_ASID > > > + }; > > > + break; > > > + case ARM_SMMU_DOMAIN_S2: > > > + *cur = (struct arm_smmu_inv){ > > > + .smmu = master->smmu, > > > + .type = INV_TYPE_S2_VMID, > > > + .id = smmu_domain->s2_cfg.vmid, > > > + .size_opcode = CMDQ_OP_TLBI_S2_IPA, > > > + .nsize_opcode = CMDQ_OP_TLBI_S12_VMALL, > > > + }; > > > + break; > > > > Having a helper to add an invalidation command would make this a little > > more compact and you could also check against the size of the array. > > Yeah but it makes all the parameters positional instead of nicely > named.. Will's remarks did raise an issue that __counted_by() requires a max_invs v.s. num_invs that can be smaller due to the removal of tailing trash entries. Then, it's probably nicer to add a check against the max_invs. I did the following, which doesn't look too bad to me: diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index b04936e76cfd..28765febf99f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3066,6 +3066,51 @@ static void arm_smmu_disable_iopf(struct arm_smmu_master *master, iopf_queue_remove_device(master->smmu->evtq.iopf, master->dev); } +static struct arm_smmu_inv * +arm_smmu_master_build_inv(struct arm_smmu_master *master, + enum arm_smmu_inv_type type, u32 id, ioasid_t ssid, + size_t pgsize) +{ + struct arm_smmu_invs *build_invs = master->build_invs; + struct arm_smmu_inv *cur, inv = { + .smmu = master->smmu, + .type = type, + .id = id, + .pgsize = pgsize, + }; + + if (WARN_ON(build_invs->num_invs >= build_invs->max_invs)) + return NULL; + cur = &build_invs->inv[build_invs->num_invs]; + build_invs->num_invs++; + + *cur = inv; + switch (type) { + case INV_TYPE_S1_ASID: + if (master->smmu->features & ARM_SMMU_FEAT_E2H) { + cur->size_opcode = CMDQ_OP_TLBI_EL2_VA; + cur->nsize_opcode = CMDQ_OP_TLBI_EL2_ASID; + } else { + cur->size_opcode = CMDQ_OP_TLBI_NH_VA; + cur->nsize_opcode = CMDQ_OP_TLBI_NH_ASID; + } + break; + case INV_TYPE_S2_VMID: + cur->size_opcode = CMDQ_OP_TLBI_S2_IPA; + cur->nsize_opcode = CMDQ_OP_TLBI_S12_VMALL; + break; + case INV_TYPE_S2_VMID_S1_CLEAR: + cur->size_opcode = cur->nsize_opcode = CMDQ_OP_TLBI_NH_ALL; + break; + case INV_TYPE_ATS: + case INV_TYPE_ATS_FULL: + cur->size_opcode = cur->nsize_opcode = CMDQ_OP_ATC_INV; + break; + } + + return cur; +} + /* * Use the preallocated scratch array at master->build_invs, to build a to_merge * or to_unref array, to pass into a following arm_smmu_invs_merge/unref() call. @@ -3077,84 +3122,58 @@ static struct arm_smmu_invs * arm_smmu_master_build_invs(struct arm_smmu_master *master, bool ats_enabled, ioasid_t ssid, struct arm_smmu_domain *smmu_domain) { - const bool e2h = master->smmu->features & ARM_SMMU_FEAT_E2H; - struct arm_smmu_invs *build_invs = master->build_invs; const bool nesting = smmu_domain->nest_parent; - struct arm_smmu_inv *cur; + size_t pgsize = 0, i; iommu_group_mutex_assert(master->dev); - cur = build_invs->inv; + master->build_invs->num_invs = 0; + + /* Range-based invalidation requires the leaf pgsize for calculation */ + if (master->smmu->features & ARM_SMMU_FEAT_RANGE_INV) + pgsize = __ffs(smmu_domain->domain.pgsize_bitmap); switch (smmu_domain->stage) { case ARM_SMMU_DOMAIN_SVA: case ARM_SMMU_DOMAIN_S1: - *cur = (struct arm_smmu_inv){ - .smmu = master->smmu, - .type = INV_TYPE_S1_ASID, - .id = smmu_domain->cd.asid, - .size_opcode = e2h ? CMDQ_OP_TLBI_EL2_VA : - CMDQ_OP_TLBI_NH_VA, - .nsize_opcode = e2h ? CMDQ_OP_TLBI_EL2_ASID : - CMDQ_OP_TLBI_NH_ASID - }; + if (!arm_smmu_master_build_inv(master, INV_TYPE_S1_ASID, + smmu_domain->cd.asid, + IOMMU_NO_PASID, pgsize)) + return NULL; break; case ARM_SMMU_DOMAIN_S2: - *cur = (struct arm_smmu_inv){ - .smmu = master->smmu, - .type = INV_TYPE_S2_VMID, - .id = smmu_domain->s2_cfg.vmid, - .size_opcode = CMDQ_OP_TLBI_S2_IPA, - .nsize_opcode = CMDQ_OP_TLBI_S12_VMALL, - }; + if (!arm_smmu_master_build_inv(master, INV_TYPE_S2_VMID, + smmu_domain->s2_cfg.vmid, + IOMMU_NO_PASID, pgsize)) + return NULL; break; default: WARN_ON(true); return NULL; } - /* Range-based invalidation requires the leaf pgsize for calculation */ - if (master->smmu->features & ARM_SMMU_FEAT_RANGE_INV) - cur->pgsize = __ffs(smmu_domain->domain.pgsize_bitmap); - cur++; - /* All the nested S1 ASIDs have to be flushed when S2 parent changes */ if (nesting) { - *cur = (struct arm_smmu_inv){ - .smmu = master->smmu, - .type = INV_TYPE_S2_VMID_S1_CLEAR, - .id = smmu_domain->s2_cfg.vmid, - .size_opcode = CMDQ_OP_TLBI_NH_ALL, - .nsize_opcode = CMDQ_OP_TLBI_NH_ALL, - }; - cur++; + if (!arm_smmu_master_build_inv( + master, INV_TYPE_S2_VMID_S1_CLEAR, + smmu_domain->s2_cfg.vmid, IOMMU_NO_PASID, 0)) + return NULL; } - if (ats_enabled) { - size_t i; - - for (i = 0; i < master->num_streams; i++) { - /* - * If an S2 used as a nesting parent is changed we have - * no option but to completely flush the ATC. - */ - *cur = (struct arm_smmu_inv){ - .smmu = master->smmu, - .type = nesting ? INV_TYPE_ATS_FULL : - INV_TYPE_ATS, - .id = master->streams[i].id, - .ssid = ssid, - .size_opcode = CMDQ_OP_ATC_INV, - .nsize_opcode = CMDQ_OP_ATC_INV, - }; - cur++; - } + for (i = 0; ats_enabled && i < master->num_streams; i++) { + /* + * If an S2 used as a nesting parent is changed we have no + * option but to completely flush the ATC. + */ + if (!arm_smmu_master_build_inv( + master, nesting ? INV_TYPE_ATS_FULL : INV_TYPE_ATS, + master->streams[i].id, ssid, 0)) + return NULL; } /* Note this build_invs must have been sorted */ - build_invs->num_invs = cur - build_invs->inv; - return build_invs; + return master->build_invs; } static void arm_smmu_remove_master_domain(struct arm_smmu_master *master, Thanks Nicolin