From: Frank Li <Frank.li@nxp.com>
To: ming.qian@oss.nxp.com
Cc: linux-media@vger.kernel.org, mchehab@kernel.org,
hverkuil-cisco@xs4all.nl, nicolas@ndufresne.ca,
benjamin.gaignard@collabora.com, p.zabel@pengutronix.de,
sebastian.fricke@collabora.com, shawnguo@kernel.org,
ulf.hansson@linaro.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
l.stach@pengutronix.de, peng.fan@nxp.com, eagle.zhou@nxp.com,
imx@lists.linux.dev, linux-pm@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 2/3] pmdomain: imx8m-blk-ctrl: Remove separate rst and clk mask for 8mq vpu
Date: Thu, 4 Dec 2025 12:24:16 -0500 [thread overview]
Message-ID: <aTHDwHKcNnesAjKP@lizhi-Precision-Tower-5810> (raw)
In-Reply-To: <20251204090813.595-2-ming.qian@oss.nxp.com>
On Thu, Dec 04, 2025 at 05:08:10PM +0800, ming.qian@oss.nxp.com wrote:
> From: Ming Qian <ming.qian@oss.nxp.com>
>
> For i.MX8MQ platform, the ADB in the VPUMIX domain has no separate reset
> and clock enable bits, but is ungated and reset together with the VPUs.
> So we can't reset G1 or G2 separately, it may led to the system hang.
> Remove rst_mask and clk_mask of imx8mq_vpu_blk_ctl_domain_data.
> Let imx8mq_vpu_power_notifier() do really vpu reset.
>
> Fixes: 608d7c325e85 ("soc: imx: imx8m-blk-ctrl: add i.MX8MQ VPU blk-ctrl")
> Signed-off-by: Ming Qian <ming.qian@oss.nxp.com>
> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
> v3
> - Add some comments
> v2
> - Update commit message
>
> drivers/pmdomain/imx/imx8m-blk-ctrl.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pmdomain/imx/imx8m-blk-ctrl.c b/drivers/pmdomain/imx/imx8m-blk-ctrl.c
> index 5c83e5599f1e..74bf4936991d 100644
> --- a/drivers/pmdomain/imx/imx8m-blk-ctrl.c
> +++ b/drivers/pmdomain/imx/imx8m-blk-ctrl.c
> @@ -846,22 +846,25 @@ static int imx8mq_vpu_power_notifier(struct notifier_block *nb,
> return NOTIFY_OK;
> }
>
> +/*
> + * For i.MX8MQ, the ADB in the VPUMIX domain has no separate reset and clock
> + * enable bits, but is ungated and reset together with the VPUs.
> + * Resetting G1 or G2 separately may led to system hang.
> + * Remove the rst_mask and clk_mask from the domain data of G1 and G2,
> + * Let imx8mq_vpu_power_notifier() do really vpu reset.
> + */
> static const struct imx8m_blk_ctrl_domain_data imx8mq_vpu_blk_ctl_domain_data[] = {
> [IMX8MQ_VPUBLK_PD_G1] = {
> .name = "vpublk-g1",
> .clk_names = (const char *[]){ "g1", },
> .num_clks = 1,
> .gpc_name = "g1",
> - .rst_mask = BIT(1),
> - .clk_mask = BIT(1),
> },
> [IMX8MQ_VPUBLK_PD_G2] = {
> .name = "vpublk-g2",
> .clk_names = (const char *[]){ "g2", },
> .num_clks = 1,
> .gpc_name = "g2",
> - .rst_mask = BIT(0),
> - .clk_mask = BIT(0),
> },
> };
>
> --
> 2.52.0
>
next prev parent reply other threads:[~2025-12-04 17:24 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-04 9:08 [PATCH v3 1/3] media: v4l2-mem2mem: Add a kref to the v4l2_m2m_dev structure ming.qian
2025-12-04 9:08 ` [PATCH v3 2/3] pmdomain: imx8m-blk-ctrl: Remove separate rst and clk mask for 8mq vpu ming.qian
2025-12-04 17:24 ` Frank Li [this message]
2025-12-04 9:08 ` [PATCH v3 3/3] media: verisilicon: Avoid G2 bus error while decoding H.264 and HEVC ming.qian
2025-12-04 17:34 ` Frank Li
2025-12-04 18:15 ` Nicolas Dufresne
2025-12-04 22:57 ` Frank Li
2025-12-05 0:05 ` Nicolas Dufresne
2025-12-05 15:07 ` Frank Li
2025-12-04 17:23 ` [PATCH v3 1/3] media: v4l2-mem2mem: Add a kref to the v4l2_m2m_dev structure Frank Li
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