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From: Nicolin Chen <nicolinc@nvidia.com>
To: Shuai Xue <xueshuai@linux.alibaba.com>
Cc: <jgg@nvidia.com>, <will@kernel.org>, <robin.murphy@arm.com>,
	<joro@8bytes.org>, <linux-arm-kernel@lists.infradead.org>,
	<iommu@lists.linux.dev>, <linux-kernel@vger.kernel.org>,
	<skolothumtho@nvidia.com>, <praan@google.com>
Subject: Re: [PATCH rc v1 4/4] iommu/arm-smmu-v3-test: Add nested s1bypass coverage
Date: Sat, 6 Dec 2025 11:50:06 -0800	[thread overview]
Message-ID: <aTSI7iFaS1BnmDg5@nvidia.com> (raw)
In-Reply-To: <703ba08f-eec0-44d8-a224-c96706df5fab@linux.alibaba.com>

On Sat, Dec 06, 2025 at 08:34:09PM +0800, Shuai Xue wrote:
> 
> 
> 在 2025/12/6 08:52, Nicolin Chen 写道:
> > STE in a nested case requires both S1 and S2 fields. And this makes the use
> > case different from the existing one.
> > 
> > Add coverage for previously failed cases shifting between S2-only and S1+S2
> > STEs.
> > 
> > Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
> > ---
> >   .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c  | 32 +++++++++++++++++++
> >   1 file changed, 32 insertions(+)
> > 
> > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c
> > index 9287904c93a2..56bdcf5a517e 100644
> > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c
> > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c
> > @@ -553,6 +553,36 @@ static void arm_smmu_v3_write_ste_test_s2_to_s1_stall(struct kunit *test)
> >   						       NUM_EXPECTED_SYNCS(3));
> >   }
> > +static void
> > +arm_smmu_v3_write_ste_test_nested_s1dssbypass_to_s1bypass(struct kunit *test)
> > +{
> > +	struct arm_smmu_ste s1_ste;
> > +	struct arm_smmu_ste s2_ste;
> > +
> > +	arm_smmu_test_make_s2_ste(&s1_ste, ARM_SMMU_MASTER_TEST_ATS);
> > +	arm_smmu_test_make_cdtable_ste(&s1_ste, STRTAB_STE_1_S1DSS_SSID0,
> 
> arm_smmu_test_make_s2_ste() makes a s2 ste and it will be overwrited by
> arm_smmu_test_make_cdtable_ste(). Finnaly, we got a s1 STE, not a nested
> s1dssbypass ste.

You are right. There is memset.

> I think we need a function like arm_smmu_make_nested_cd_table_ste()
> here.
> 
> Besides, from the function name, I think you mean
> STRTAB_STE_1_S1DSS_BYPASS?

Yes, I will fix these.

Thanks
Nicolin


      parent reply	other threads:[~2025-12-06 19:50 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-06  0:51 [PATCH rc v1 0/4] iommu/arm-smmu-v3: Fix hitless STE update in nesting cases Nicolin Chen
2025-12-06  0:52 ` [PATCH rc v1 1/4] iommu/arm-smmu-v3: Add ignored bits to fix STE update sequence Nicolin Chen
2025-12-06 14:19   ` Shuai Xue
2025-12-06 19:38     ` Jason Gunthorpe
2025-12-06 19:34   ` Jason Gunthorpe
2025-12-06 19:45     ` Nicolin Chen
2025-12-06 19:57       ` Jason Gunthorpe
2025-12-07  4:37         ` Nicolin Chen
2025-12-07 16:09           ` Jason Gunthorpe
2025-12-07 19:35             ` Nicolin Chen
2025-12-07 20:11               ` Nicolin Chen
2025-12-06  0:52 ` [PATCH rc v1 2/4] iommu/arm-smmu-v3: Ignore STE MEV when computing the " Nicolin Chen
2025-12-06  0:52 ` [PATCH rc v1 3/4] iommu/arm-smmu-v3: Ignore STE EATS " Nicolin Chen
2025-12-06 19:46   ` Jason Gunthorpe
2025-12-06 19:54     ` Nicolin Chen
2025-12-06  0:52 ` [PATCH rc v1 4/4] iommu/arm-smmu-v3-test: Add nested s1bypass coverage Nicolin Chen
2025-12-06 12:34   ` Shuai Xue
2025-12-06 19:42     ` Jason Gunthorpe
2025-12-06 19:50     ` Nicolin Chen [this message]

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