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Sat, 6 Dec 2025 20:37:32 -0800 Date: Sat, 6 Dec 2025 20:37:30 -0800 From: Nicolin Chen To: Jason Gunthorpe CC: , , , , , , , Subject: Re: [PATCH rc v1 1/4] iommu/arm-smmu-v3: Add ignored bits to fix STE update sequence Message-ID: References: <6ec73bb7cd03d90a0764f12c4b14071158163818.1764982046.git.nicolinc@nvidia.com> <20251206193408.GD1219718@nvidia.com> <20251206195752.GI1219718@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20251206195752.GI1219718@nvidia.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F6:EE_|CH3PR12MB8754:EE_ X-MS-Office365-Filtering-Correlation-Id: 2e8adf79-6f4e-4836-0b2c-08de354a57b2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?WU6Gp9AnL/OXjZasDSJYzQm48KKBqt6I4bZshKFtchNgfSjbK4jBdeeI3pji?= =?us-ascii?Q?F5yYFbVTAzFyFK6UIgMLFExVakPTmZNKx8Xo6udUwUqBuY74KrijURv0MP3m?= =?us-ascii?Q?qfX9S2i4D7dXu5fa6kMzq7OFzOcl5bnAAbhRgCJdavmxrTU+TSxLvPBEzn9U?= =?us-ascii?Q?ge3Y74dSFlYA4vgu2jc++RWsrVZDh8nWkPb1umdI1CnawjObZkgNUyb4lJtX?= =?us-ascii?Q?rWIYDJYWm/UmdwDkWhEwYQgAEBkh4bvnbrX7p/PVoN0paYuqsQ1sCQpH2PjD?= =?us-ascii?Q?aVG2pAY/7XSWmWlA86rDG5wcSzaKvZ5HETS760PYPzf5pcT0xD/CrAx2dd53?= =?us-ascii?Q?uzogoov5Bd5nd5YCYM6DCbMgSbNXJgRhyqGBlhgFs0vIkRhBAs46HJuUv61g?= =?us-ascii?Q?NgcNgFIMsNSB83MVnk3BPvldkpxzv4i+GKXLZkLOCvKCa0nwBAF2mTnm3PPW?= =?us-ascii?Q?iFtXSbnCEvv6HXgak0PhLiGRz8ZmPenctUbPu796HSStEWW+MhaPPbwHNC5m?= =?us-ascii?Q?T5oxZAKJtJufGnymFmJ5pAdj830yjbhnO1C1Fs7GH7yz8h8jVIJi0MKzAEec?= =?us-ascii?Q?XqvkS+Wib7wWibcP3xMIj52OfySYWa9cg42vURfqE4qswFY7rvQJfJt81jEW?= =?us-ascii?Q?ZKC1zPITi0j6N8yMEb999KGaIANiYaofhJ8lFGDOD3XvCJxwQgymJ4yl+/C6?= =?us-ascii?Q?ZI+sWbFlEm4Ksc+A7Srjqxlif2hnSARwaTqGRDHQxTtA3stDlQ6EJ5/UORgn?= =?us-ascii?Q?WgEVTtCrbIk87484llyFOr0s3i1YPLUumduG/QaKU/vRYWVcA+Sc69Xbb/eh?= =?us-ascii?Q?tk54lZCo8agxOS/mrS2OkY2GOqJLu4ABBoAkCt6o9499AwihkT2xcEPt9Scy?= =?us-ascii?Q?lALqdzKnrMp10rwyQE9/Mrk1+5ZS6xdxyb+GLJdHmmTjx14RZ8G7Z6T5vg5M?= =?us-ascii?Q?qAajEvlumc7fDKSP9wPFa81JJLksSsIKF9I2C+kRqLVKBoxFdBRaxtUm7/lm?= =?us-ascii?Q?QglpIMy1EdSSgzAFRxgOrpfijUljIMCO6Q+3oJGAcxGhplSspBjUr56owjGs?= =?us-ascii?Q?nVyGm5SYlAO3WIcOGI0OpV/2HqZ2YhWwAt4IxUQWx+eXolYBal/1U7DmHbzJ?= =?us-ascii?Q?5WJLurZk/D/QUsZXe0sJEQZrLQjDcnGettdZ2e2KvskR+yyt6ABmOLZUvTLS?= =?us-ascii?Q?3R85H11N5vXaaWVlJe/91dGOI/MF2eFmucpcehd89x3grP73NN90d+RfV7xW?= =?us-ascii?Q?vpp4djJpGWWuaWYbNWQyPXZs6MH3QCQFREOcLraBAdysn/BD1w1+u/kKgDys?= =?us-ascii?Q?TsmXpvC3scTF/5GBOAxp2qJha0DGeqxwffPkGvIJ3u5E8/GdfadNmOv1riR+?= =?us-ascii?Q?3PGSR/b9B4PbjJyGKAqJRXGcEqksdOsieAoDDJulydumPR1vTZ/6ZSzGJ/mo?= =?us-ascii?Q?G+RVHJ2eLLA7nyRtv0IEJG4q/X5TzT5gfnv3xv7KsjNAKagW9C4fDE5iMBFM?= =?us-ascii?Q?Xl9cOy2FQXT5+XCmi7lTxGNtnCfXGAAnFqthvP2IlhQjI2xACg45KESCSQje?= =?us-ascii?Q?SgVJ/1o7ZWpGA52C69E=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Dec 2025 04:37:34.8133 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2e8adf79-6f4e-4836-0b2c-08de354a57b2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8754 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251206_203741_887070_3D295A39 X-CRM114-Status: GOOD ( 16.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Dec 06, 2025 at 03:57:52PM -0400, Jason Gunthorpe wrote: > I think that supports more that we should do what Shuai suggested and > keep used as-is. Yes, that will be probably cleaner. > Then ignored should be adjusted by the used: Only if both used are 1 > should the bit become ignored. Otherwise we can rely on which ever > used is 0 to generate the hitless update. Hmm, not sure why it has to be both used. The unused_update is computed using cur_used, and the equation for used_qword_diff is computed using target_used, either of which can be affected by ignored bits, right? E.g. if cur_used[] includes ING bit, target_used doesn't: // target must unset IGN bit, last equation isn't affected if cur sets IGN bit cur_used should exclude IGN bit if cur unsets IGN bit not affected if cur_used[] doesn't include ignores, target_used does: // cur must unset IGN bit, cur_used isn't affected if target sets IGN bit: last equation must exclude IGN bit on both sides if target unsets IGN bit: not affected > @@ -1109,6 +1118,7 @@ static u8 arm_smmu_entry_qword_diff(struct arm_smmu_entry_writer *writer, > WARN_ON_ONCE(target[i] & ~target_used[i]); > > /* Bits can change because they are not currently being used */ > + cur_used[i] &= ~ignored[i]; > unused_update[i] = (entry[i] & cur_used[i]) | > (target[i] & ~cur_used[i]); If one of ignored bits is set in entry[i] but unset in target[i], the unused_update will first mask it away, resulting in an extra unnecessary update (though it's still hitless). So, I think this might be better: - cur_used[i] &= ~ignored[i]; + cur_unused[i] = ~cur_used[i] | ignored[i]; unused_update[i] = (entry[i] & cur_used[i]) | - (target[i] & ~cur_used[i]); + (target[i] & cur_unused[i]); Because cur_used includes ignored, the unused_update will retain the ignored bits from entry. On the other hand, having cur_unused will also retain the ignored bits from target. One more change that we need is at the last equation: - if ((unused_update[i] & target_used[i]) != target[i]) + if ((unused_update[i] & target_used[i] & ~ignored[i]) != + (target[i] & ~ignored[i])) Either side might have the ignored bits, so we have to suppress ignored on both sides, which is required in the similar routine in arm_smmu_entry_differs_in_used_bits() of the kunit code. With these additional changes, nesting sanity and kunit test are both passing. I will do a few more tests to make sure things are okay, before wrapping up the v2. Please let me know if all these make sense to you. Thanks Nicolin