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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2025 20:51:24.9821 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 026cbcf4-cc7d-42c5-d486-08de3c1bb617 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5740 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251215_125132_173880_C9A7EBCC X-CRM114-Status: GOOD ( 24.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Mostafa, On Sun, Dec 14, 2025 at 10:32:35PM +0000, Mostafa Saleh wrote: > On Tue, Dec 09, 2025 at 06:45:16PM -0800, Nicolin Chen wrote: > > @@ -1207,12 +1223,9 @@ void arm_smmu_write_entry(struct arm_smmu_entry_writer *writer, __le64 *entry, > > entry_set(writer, entry, target, 0, 1); > > } else { > > /* > > - * No inuse bit changed. Sanity check that all unused bits are 0 > > - * in the entry. The target was already sanity checked by > > - * compute_qword_diff(). > > + * No inuse bit changed, though ignored bits may have changed. > > */ > > - WARN_ON_ONCE( > > - entry_set(writer, entry, target, 0, NUM_ENTRY_QWORDS)); > > + entry_set(writer, entry, target, 0, NUM_ENTRY_QWORDS); > > After this change, no other caller uses the entry_set() return value, so it > can be changed to return void. OK. > > } > > } > > EXPORT_SYMBOL_IF_KUNIT(arm_smmu_write_entry); > > @@ -1543,6 +1556,7 @@ static void arm_smmu_ste_writer_sync_entry(struct arm_smmu_entry_writer *writer) > > static const struct arm_smmu_entry_writer_ops arm_smmu_ste_writer_ops = { > > .sync = arm_smmu_ste_writer_sync_entry, > > .get_used = arm_smmu_get_ste_used, > > + .get_ignored = arm_smmu_get_ste_ignored, > > }; > > > > I have some mixed feelings about this, having get_used(), then get_ignored() > with the same bits set seems confusing to me, specially the get_ignored() > loops back to update cur_used, which is set from get_used() > > My initial though was just to remove this bit from get_used() + some changes > to checks setting bits that are not used would be enough, and the semantics > of get_used() can be something as: > “Return bits used by the updated translation regime that MUST be observed > atomically” and in that case we can ignore things as MEV as it doesn’t > impact the translation. > > However, this approach makes it a bit explicit which bits are ignored, if we > keep this logic, I think changing the name of get_ignored() might help, to > something as "get_allowed_break()" or "get_update_safe()"? I think "ignored" itself is brief and understandable.. Instead, perhaps we can add a kdocs to make it clearer: /** * struct arm_smmu_entry_writer_ops - STE/CD entry writer operations * @get_used: Output to @used the bits used by the hardware corresponding to the * configurations bits set in a given @entry * @get_ignored: Output to @ignored the bits that are listed in the "used" list * but allowed to be ignored by arm_smmu_entry_qword_diff(). Each * field (bits) must provide a reason to justify that the entries * can be updated safely without breaking STE/CD configurations. * @sync: Operation to synchronize the updated STE/CD entries in the memory */ struct arm_smmu_entry_writer_ops { void (*get_used)(const __le64 *entry, __le64 *used); void (*get_ignored)(__le64 *ignored); void (*sync)(struct arm_smmu_entry_writer *writer); }; ? Thanks Nicolin