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Miller" , devicetree@vger.kernel.org, Eric Dumazet , Fabio Estevam , Ghennadi Procopciuc , imx@lists.linux.dev, Jakub Kicinski , Jan Petrous , Krzysztof Kozlowski , Lee Jones , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Matthias Brugger , Maxime Coquelin , netdev@vger.kernel.org, NXP S32 Linux Team , Paolo Abeni , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , linaro-s32@linaro.org Subject: Re: [PATCH v2 0/4] s32g: Use a syscon for GPR Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251215_103400_975405_B7BEA780 X-CRM114-Status: GOOD ( 27.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Dec 15, 2025 at 10:56:49AM -0500, Frank Li wrote: > On Mon, Dec 15, 2025 at 05:41:43PM +0300, Dan Carpenter wrote: > > The s32g devices have a GPR register region which holds a number of > > miscellaneous registers. Currently only the stmmac/dwmac-s32.c uses > > anything from there and we just add a line to the device tree to > > access that GMAC_0_CTRL_STS register: > > > > reg = <0x4033c000 0x2000>, /* gmac IP */ > > <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ > > > > We still have to maintain backwards compatibility to this format, > > of course, but it would be better to access these through a syscon. > > First of all, putting all the registers together is more organized > > and shows how the hardware actually is implemented. Secondly, in > > some versions of this chipset those registers can only be accessed > > via SCMI, if the registers aren't grouped together each driver will > > have to create a whole lot of if then statements to access it via > > IOMEM or via SCMI, > > Does SCMI work as regmap? syscon look likes simple, but missed abstract > in overall. > The SCMI part of this is pretty complicated and needs discussion. It might be that it requires a vendor extension. Right now, the out of tree code uses a nvmem vendor extension but that probably won't get merged upstream. But in theory, it's fairly simple, you can write a regmap driver and register it as a syscon and everything that was accessing nxp,phy-sel accesses the same register but over SCMI. > You still use regmap by use MMIO. /* GMAC_0_CTRL_STS */ > > regmap = devm_regmap_init_mmio(dev, sts_offset, ®map_config); > You can use have an MMIO syscon, or you can create a custom driver and register it as a syscon using of_syscon_register_regmap(). > So all code can use regmap function without if-then statements if SCMI work > as regmap. > regards, dan carpenter