From: Linu Cherian <linu.cherian@arm.com>
To: Ryan Roberts <ryan.roberts@arm.com>
Cc: Will Deacon <will@kernel.org>, Ard Biesheuvel <ardb@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Linus Torvalds <torvalds@linux-foundation.org>,
Oliver Upton <oliver.upton@linux.dev>,
Marc Zyngier <maz@kernel.org>, Dev Jain <dev.jain@arm.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 03/13] arm64: mm: Implicitly invalidate user ASID based on TLBI operation
Date: Thu, 18 Dec 2025 12:00:53 +0530 [thread overview]
Message-ID: <aUOfnXnGVROEXH4r@a079125.arm.com> (raw)
In-Reply-To: <20251216144601.2106412-4-ryan.roberts@arm.com>
Ryan,
On Tue, Dec 16, 2025 at 02:45:48PM +0000, Ryan Roberts wrote:
> When kpti is enabled, separate ASIDs are used for userspace and
> kernelspace, requiring ASID-qualified TLB invalidation by virtual
> address to invalidate both of them.
>
> Push the logic for invalidating the two ASIDs down into the low-level
> tlbi-op-specific functions and remove the burden from the caller to
> handle the kpti-specific behaviour.
>
> Co-developed-by: Will Deacon <will@kernel.org>
> Signed-off-by: Will Deacon <will@kernel.org>
> Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
> ---
> arch/arm64/include/asm/tlbflush.h | 27 ++++++++++-----------------
> 1 file changed, 10 insertions(+), 17 deletions(-)
>
> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
> index c5111d2afc66..31f43d953ce2 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -110,6 +110,7 @@ typedef void (*tlbi_op)(u64 arg);
> static __always_inline void vae1is(u64 arg)
> {
> __tlbi(vae1is, arg);
> + __tlbi_user(vae1is, arg);
> }
>
> static __always_inline void vae2is(u64 arg)
> @@ -126,6 +127,7 @@ static __always_inline void vale1(u64 arg)
> static __always_inline void vale1is(u64 arg)
> {
> __tlbi(vale1is, arg);
> + __tlbi_user(vale1is, arg);
> }
>
> static __always_inline void vale2is(u64 arg)
> @@ -162,11 +164,6 @@ static __always_inline void __tlbi_level(tlbi_op op, u64 addr, u32 level)
> op(arg);
> }
>
> -#define __tlbi_user_level(op, arg, level) do { \
> - if (arm64_kernel_unmapped_at_el0()) \
> - __tlbi_level(op, (arg | USER_ASID_FLAG), level); \
> -} while (0)
> -
> /*
> * This macro creates a properly formatted VA operand for the TLB RANGE. The
> * value bit assignments are:
> @@ -435,8 +432,6 @@ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch)
> * @stride: Flush granularity
> * @asid: The ASID of the task (0 for IPA instructions)
> * @tlb_level: Translation Table level hint, if known
> - * @tlbi_user: If 'true', call an additional __tlbi_user()
> - * (typically for user ASIDs). 'flase' for IPA instructions
> * @lpa2: If 'true', the lpa2 scheme is used as set out below
> *
> * When the CPU does not support TLB range operations, flush the TLB
> @@ -462,6 +457,7 @@ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch)
> static __always_inline void rvae1is(u64 arg)
> {
> __tlbi(rvae1is, arg);
> + __tlbi_user(rvae1is, arg);
> }
>
> static __always_inline void rvale1(u64 arg)
> @@ -473,6 +469,7 @@ static __always_inline void rvale1(u64 arg)
> static __always_inline void rvale1is(u64 arg)
> {
> __tlbi(rvale1is, arg);
> + __tlbi_user(rvale1is, arg);
> }
>
> static __always_inline void rvaale1is(u64 arg)
> @@ -491,7 +488,7 @@ static __always_inline void __tlbi_range(tlbi_op op, u64 arg)
> }
>
> #define __flush_tlb_range_op(op, start, pages, stride, \
> - asid, tlb_level, tlbi_user, lpa2) \
> + asid, tlb_level, lpa2) \
> do { \
> typeof(start) __flush_start = start; \
> typeof(pages) __flush_pages = pages; \
> @@ -506,8 +503,6 @@ do { \
> (lpa2 && __flush_start != ALIGN(__flush_start, SZ_64K))) { \
> addr = __TLBI_VADDR(__flush_start, asid); \
> __tlbi_level(op, addr, tlb_level); \
> - if (tlbi_user) \
> - __tlbi_user_level(op, addr, tlb_level); \
> __flush_start += stride; \
> __flush_pages -= stride >> PAGE_SHIFT; \
> continue; \
> @@ -518,8 +513,6 @@ do { \
> addr = __TLBI_VADDR_RANGE(__flush_start >> shift, asid, \
> scale, num, tlb_level); \
> __tlbi_range(r##op, addr); \
> - if (tlbi_user) \
> - __tlbi_user(r##op, addr); \
> __flush_start += __TLBI_RANGE_PAGES(num, scale) << PAGE_SHIFT; \
> __flush_pages -= __TLBI_RANGE_PAGES(num, scale);\
There are more __tlbi_user invocations in __flush_tlb_mm, __local_flush_tlb_page_nonotify_nosync
and __flush_tlb_page_nosync in this file. Should we not address them as well as
part of this ?
--
Linu Cherian.
next prev parent reply other threads:[~2025-12-18 6:31 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-16 14:45 [PATCH v1 00/13] arm64: Refactor TLB invalidation API and implementation Ryan Roberts
2025-12-16 14:45 ` [PATCH v1 01/13] arm64: mm: Re-implement the __tlbi_level macro as a C function Ryan Roberts
2025-12-16 17:53 ` Jonathan Cameron
2026-01-02 14:18 ` Ryan Roberts
2025-12-16 14:45 ` [PATCH v1 02/13] arm64: mm: Introduce a C wrapper for by-range TLB invalidation Ryan Roberts
2025-12-16 14:45 ` [PATCH v1 03/13] arm64: mm: Implicitly invalidate user ASID based on TLBI operation Ryan Roberts
2025-12-16 18:01 ` Jonathan Cameron
2026-01-02 14:20 ` Ryan Roberts
2025-12-18 6:30 ` Linu Cherian [this message]
2025-12-18 7:05 ` Linu Cherian
2025-12-18 15:47 ` Linu Cherian
2026-01-02 14:30 ` Ryan Roberts
2025-12-16 14:45 ` [PATCH v1 04/13] arm64: mm: Push __TLBI_VADDR() into __tlbi_level() Ryan Roberts
2025-12-16 14:45 ` [PATCH v1 05/13] arm64: mm: Inline __TLBI_VADDR_RANGE() into __tlbi_range() Ryan Roberts
2025-12-16 14:45 ` [PATCH v1 06/13] arm64: mm: Re-implement the __flush_tlb_range_op macro in C Ryan Roberts
2025-12-16 14:45 ` [PATCH v1 07/13] arm64: mm: Simplify __TLBI_RANGE_NUM() macro Ryan Roberts
2025-12-16 14:45 ` [PATCH v1 08/13] arm64: mm: Simplify __flush_tlb_range_limit_excess() Ryan Roberts
2025-12-17 8:12 ` Dev Jain
2026-01-02 15:23 ` Ryan Roberts
2025-12-16 14:45 ` [PATCH v1 09/13] arm64: mm: Refactor flush_tlb_page() to use __tlbi_level_asid() Ryan Roberts
2025-12-16 14:45 ` [PATCH v1 10/13] arm64: mm: Refactor __flush_tlb_range() to take flags Ryan Roberts
2025-12-16 14:45 ` [PATCH v1 11/13] arm64: mm: More flags for __flush_tlb_range() Ryan Roberts
2025-12-16 14:45 ` [PATCH v1 12/13] arm64: mm: Wrap flush_tlb_page() around ___flush_tlb_range() Ryan Roberts
2025-12-16 14:45 ` [PATCH v1 13/13] arm64: mm: Provide level hint for flush_tlb_page() Ryan Roberts
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=aUOfnXnGVROEXH4r@a079125.arm.com \
--to=linu.cherian@arm.com \
--cc=ardb@kernel.org \
--cc=catalin.marinas@arm.com \
--cc=dev.jain@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=maz@kernel.org \
--cc=oliver.upton@linux.dev \
--cc=ryan.roberts@arm.com \
--cc=torvalds@linux-foundation.org \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).