From: Mostafa Saleh <smostafa@google.com>
To: Nicolin Chen <nicolinc@nvidia.com>
Cc: jgg@nvidia.com, will@kernel.org, robin.murphy@arm.com,
joro@8bytes.org, linux-arm-kernel@lists.infradead.org,
iommu@lists.linux.dev, linux-kernel@vger.kernel.org,
skolothumtho@nvidia.com, praan@google.com,
xueshuai@linux.alibaba.com
Subject: Re: [PATCH rc v4 2/4] iommu/arm-smmu-v3: Mark STE MEV safe when computing the update sequence
Date: Thu, 18 Dec 2025 16:40:30 +0000 [thread overview]
Message-ID: <aUQufkkJYrOp0erD@google.com> (raw)
In-Reply-To: <83f991cbbb1331213aabe7c1fc5f725e79f60ecd.1765945258.git.nicolinc@nvidia.com>
On Tue, Dec 16, 2025 at 08:26:00PM -0800, Nicolin Chen wrote:
> From: Jason Gunthorpe <jgg@nvidia.com>
>
> Nested CD tables set the MEV bit to try to reduce multi-fault spamming on
> the hypervisor. Since MEV is in STE word 1 this causes a breaking update
> sequence that is not required and impacts real workloads.
>
> For the purposes of STE updates the value of MEV doesn't matter, if it is
> set/cleared early or late it just results in a change to the fault reports
> that must be supported by the kernel anyhow. The spec says:
>
> Note: Software must expect, and be able to deal with, coalesced fault
> records even when MEV == 0.
>
> So mark STE MEV safe when computing the update sequence, to avoid creating
> a breaking update.
>
> Fixes: da0c56520e88 ("iommu/arm-smmu-v3: Set MEV bit in nested STE for DoS mitigations")
> Cc: stable@vger.kernel.org
> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
> Reviewed-by: Shuai Xue <xueshuai@linux.alibaba.com>
> Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
> ---
> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Thanks,
Mostafa
>
> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> index 8dbf4ad5b51e..12a9669bcc83 100644
> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> @@ -1085,6 +1085,16 @@ EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_used);
> VISIBLE_IF_KUNIT
> void arm_smmu_get_ste_update_safe(__le64 *safe_bits)
> {
> + /*
> + * MEV does not meaningfully impact the operation of the HW, it only
> + * changes how many fault events are generated, thus we can relax it
> + * when computing the ordering. The spec notes the device can act like
> + * MEV=1 anyhow:
> + *
> + * Note: Software must expect, and be able to deal with, coalesced
> + * fault records even when MEV == 0.
> + */
> + safe_bits[1] |= cpu_to_le64(STRTAB_STE_1_MEV);
> }
> EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_update_safe);
>
> --
> 2.43.0
>
next prev parent reply other threads:[~2025-12-18 16:40 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-17 4:25 [PATCH rc v4 0/4] iommu/arm-smmu-v3: Fix hitless STE update in nesting cases Nicolin Chen
2025-12-17 4:25 ` [PATCH rc v4 1/4] iommu/arm-smmu-v3: Add update_safe bits to fix STE update sequence Nicolin Chen
2025-12-18 16:40 ` Mostafa Saleh
2025-12-19 6:05 ` Nicolin Chen
2025-12-17 4:26 ` [PATCH rc v4 2/4] iommu/arm-smmu-v3: Mark STE MEV safe when computing the " Nicolin Chen
2025-12-18 16:40 ` Mostafa Saleh [this message]
2025-12-17 4:26 ` [PATCH rc v4 3/4] iommu/arm-smmu-v3: Mark STE EATS " Nicolin Chen
2025-12-18 16:42 ` Mostafa Saleh
2025-12-18 17:32 ` Nicolin Chen
2025-12-18 18:01 ` Jason Gunthorpe
2025-12-17 4:26 ` [PATCH rc v4 4/4] iommu/arm-smmu-v3-test: Add nested s1bypass/s1dssbypass coverage Nicolin Chen
2025-12-18 16:47 ` Mostafa Saleh
2025-12-18 17:35 ` Nicolin Chen
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