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[104.155.85.171]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-432449adac0sm6085692f8f.42.2025.12.18.08.42.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 08:42:43 -0800 (PST) Date: Thu, 18 Dec 2025 16:42:40 +0000 From: Mostafa Saleh To: Nicolin Chen Cc: jgg@nvidia.com, will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, skolothumtho@nvidia.com, praan@google.com, xueshuai@linux.alibaba.com Subject: Re: [PATCH rc v4 3/4] iommu/arm-smmu-v3: Mark STE EATS safe when computing the update sequence Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251218_084246_250091_A66DD134 X-CRM114-Status: GOOD ( 27.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Dec 16, 2025 at 08:26:01PM -0800, Nicolin Chen wrote: > From: Jason Gunthorpe > > If a VM wants to toggle EATS off at the same time as changing the CFG, the > hypervisor will see EATS change to 0 and insert a V=0 breaking update into > the STE even though the VM did not ask for that. > > In bare metal, EATS is ignored by CFG=ABORT/BYPASS, which is why this does > not cause a problem until we have nested where CFG is always a variation of > S2 trans that does use EATS. > > Relax the rules for EATS sequencing, we don't need it to be exact because > the enclosing code will always disable ATS at the PCI device if we are > changing EATS. This ensures there are no ATS transactions that can race > with an EATS change so we don't need to carefully sequence these bits. > > Fixes: 1e8be08d1c91 ("iommu/arm-smmu-v3: Support IOMMU_DOMAIN_NESTED") > Cc: stable@vger.kernel.org > Signed-off-by: Jason Gunthorpe > Reviewed-by: Shuai Xue > Signed-off-by: Nicolin Chen > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 12a9669bcc83..a3b29ad20a82 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -1095,6 +1095,15 @@ void arm_smmu_get_ste_update_safe(__le64 *safe_bits) > * fault records even when MEV == 0. > */ > safe_bits[1] |= cpu_to_le64(STRTAB_STE_1_MEV); > + > + /* > + * EATS is used to reject and control the ATS behavior of the device. If > + * we are changing it away from 0 then we already trust the device to > + * use ATS properly and we have sequenced the device's ATS enable in PCI > + * config space to prevent it from issuing ATS while we are changing > + * EATS. > + */ I am not sure about this one, Is it only about trusting the device? I’d be worried about cases where we switch domains, that means that briefly the HW observers EATS=1 while it was not intended, especially that EATS is in a different DWORD from S2TTB and CDptr. With all the IOMMUFD/VFIO stuff it makes it harder to reason about. But I can’t come up with an example to break this. Thanks, Mostafa > + safe_bits[1] |= cpu_to_le64(STRTAB_STE_1_EATS); > } > EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_update_safe); > > -- > 2.43.0 >