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[104.155.85.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47be3ac4c1esm16379985e9.14.2025.12.18.08.47.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 08:47:41 -0800 (PST) Date: Thu, 18 Dec 2025 16:47:38 +0000 From: Mostafa Saleh To: Nicolin Chen Cc: jgg@nvidia.com, will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, skolothumtho@nvidia.com, praan@google.com, xueshuai@linux.alibaba.com Subject: Re: [PATCH rc v4 4/4] iommu/arm-smmu-v3-test: Add nested s1bypass/s1dssbypass coverage Message-ID: References: <6fcdd663d62dcab4005401bac2d23d18dd28e0c4.1765945258.git.nicolinc@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <6fcdd663d62dcab4005401bac2d23d18dd28e0c4.1765945258.git.nicolinc@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251218_084745_272772_8C9FDAC8 X-CRM114-Status: GOOD ( 20.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Dec 16, 2025 at 08:26:02PM -0800, Nicolin Chen wrote: > STE in a nested case requires both S1 and S2 fields. And this makes the use > case different from the existing one. > > Add coverage for previously failed cases shifting between S2-only and S1+S2 > STEs. > > Reviewed-by: Shuai Xue > Signed-off-by: Nicolin Chen > --- > .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 46 +++++++++++++++++++ > 1 file changed, 46 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c > index 5db14718fdd6..8255a02f4efa 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c > @@ -33,8 +33,12 @@ static struct mm_struct sva_mm = { > enum arm_smmu_test_master_feat { > ARM_SMMU_MASTER_TEST_ATS = BIT(0), > ARM_SMMU_MASTER_TEST_STALL = BIT(1), > + ARM_SMMU_MASTER_TEST_NESTED = BIT(2), > }; > > +static void arm_smmu_test_make_s2_ste(struct arm_smmu_ste *ste, > + enum arm_smmu_test_master_feat feat); > + > static bool arm_smmu_entry_differs_in_used_bits(const __le64 *entry, > const __le64 *used_bits, > const __le64 *target, > @@ -197,6 +201,17 @@ static void arm_smmu_test_make_cdtable_ste(struct arm_smmu_ste *ste, > }; > > arm_smmu_make_cdtable_ste(ste, &master, ats_enabled, s1dss); > + if (feat & ARM_SMMU_MASTER_TEST_NESTED) { > + struct arm_smmu_ste s2ste; > + int i; > + > + arm_smmu_test_make_s2_ste(&s2ste, ARM_SMMU_MASTER_TEST_ATS); Shouldn't that be conditional on "ats_enabled", I see the callers of the new tests already set ARM_SMMU_MASTER_TEST_ATS. Thanks, Mostafa > + ste->data[0] |= cpu_to_le64( > + FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_NESTED)); > + ste->data[1] |= cpu_to_le64(STRTAB_STE_1_MEV); > + for (i = 2; i < NUM_ENTRY_QWORDS; i++) > + ste->data[i] = s2ste.data[i]; > + } > } > > static void arm_smmu_v3_write_ste_test_bypass_to_abort(struct kunit *test) > @@ -554,6 +569,35 @@ static void arm_smmu_v3_write_ste_test_s2_to_s1_stall(struct kunit *test) > NUM_EXPECTED_SYNCS(3)); > } > > +static void > +arm_smmu_v3_write_ste_test_nested_s1dssbypass_to_s1bypass(struct kunit *test) > +{ > + struct arm_smmu_ste s1_ste; > + struct arm_smmu_ste s2_ste; > + > + arm_smmu_test_make_cdtable_ste( > + &s1_ste, STRTAB_STE_1_S1DSS_BYPASS, fake_cdtab_dma_addr, > + ARM_SMMU_MASTER_TEST_ATS | ARM_SMMU_MASTER_TEST_NESTED); > + arm_smmu_test_make_s2_ste(&s2_ste, 0); > + /* Expect an additional sync to unset ignored bits: EATS and MEV */ > + arm_smmu_v3_test_ste_expect_hitless_transition(test, &s1_ste, &s2_ste, > + NUM_EXPECTED_SYNCS(3)); > +} > + > +static void > +arm_smmu_v3_write_ste_test_nested_s1bypass_to_s1dssbypass(struct kunit *test) > +{ > + struct arm_smmu_ste s1_ste; > + struct arm_smmu_ste s2_ste; > + > + arm_smmu_test_make_cdtable_ste( > + &s1_ste, STRTAB_STE_1_S1DSS_BYPASS, fake_cdtab_dma_addr, > + ARM_SMMU_MASTER_TEST_ATS | ARM_SMMU_MASTER_TEST_NESTED); > + arm_smmu_test_make_s2_ste(&s2_ste, 0); > + arm_smmu_v3_test_ste_expect_hitless_transition(test, &s2_ste, &s1_ste, > + NUM_EXPECTED_SYNCS(2)); > +} > + > static void arm_smmu_v3_write_cd_test_sva_clear(struct kunit *test) > { > struct arm_smmu_cd cd = {}; > @@ -600,6 +644,8 @@ static struct kunit_case arm_smmu_v3_test_cases[] = { > KUNIT_CASE(arm_smmu_v3_write_cd_test_s1_change_asid), > KUNIT_CASE(arm_smmu_v3_write_ste_test_s1_to_s2_stall), > KUNIT_CASE(arm_smmu_v3_write_ste_test_s2_to_s1_stall), > + KUNIT_CASE(arm_smmu_v3_write_ste_test_nested_s1dssbypass_to_s1bypass), > + KUNIT_CASE(arm_smmu_v3_write_ste_test_nested_s1bypass_to_s1dssbypass), > KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_clear), > KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_release), > {}, > -- > 2.43.0 >