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Mon, 05 Jan 2026 09:58:27 -0800 (PST) Received: from eichest-laptop ([2a02:168:af72:0:1b36:ec4b:aa3c:60f8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47d7f390a69sm703765e9.0.2026.01.05.09.58.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jan 2026 09:58:26 -0800 (PST) Date: Mon, 5 Jan 2026 18:58:24 +0100 From: Stefan Eichenberger To: "Russell King (Oracle)" Cc: Andrew Lunn , Maxime Chevallier , andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, linux-stm32@st-md-mailman.stormreply.com, netdev@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, francesco.dolcini@toradex.com, robh@kernel.org, Stefan Eichenberger Subject: Re: [PATCH RESEND net-next v2] net: stmmac: dwmac: Add a fixup for the Micrel KSZ9131 PHY Message-ID: References: <20260105100245.19317-1-eichest@gmail.com> <6ee0d55a-69de-4c28-8d9d-d7755d5c0808@bootlin.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260105_095829_322495_521CBC3B X-CRM114-Status: GOOD ( 29.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jan 05, 2026 at 05:09:13PM +0000, Russell King (Oracle) wrote: > On Mon, Jan 05, 2026 at 05:42:23PM +0100, Stefan Eichenberger wrote: > > Yes this is correct. ERR050694 from NXP states: > > The IEEE 802.3 standard states that, in MII/GMII modes, the byte > > preceding the SFD (0xD5), SMD-S (0xE6,0x4C, 0x7F, or 0xB3), or SMD-C > > (0x61, 0x52, 0x9E, or 0x2A) byte can be a non-PREAMBLE byte or there can > > be no preceding preamble byte. The MAC receiver must successfully > > receive a packet without any preamble(0x55) byte preceding the SFD, > > SMD-S, or SMD-C byte. > > However due to the defect, in configurations where frame preemption is > > enabled, when preamble byte does not precede the SFD, SMD-S, or SMD-C > > byte, the received packet is discarded by the MAC receiver. This is > > because, the start-of-packet detection logic of the MAC receiver > > incorrectly checks for a preamble byte. > > > > NXP refers to IEEE 802.3 where in clause 35.2.3.2.2 Receive case (GMII) > > they show two tables one where the preamble is preceding the SFD and one > > where it is not. The text says: > > The operation of 1000 Mb/s PHYs can result in shrinkage of the preamble > > between transmission at the source GMII and reception at the destination > > GMII. Table 35–3 depicts the case where no preamble bytes are conveyed > > across the GMII. This case may not be possible with a specific PHY, but > > illustrates the minimum preamble with which MAC shall be able to > > operate. Table 35–4 depicts the case where the entire preamble is > > conveyed across the GMII. > > > > We would change the behavior from "no preamble is preceding SFD" to "the > > enitre preamble is preceding SFD". Both are listed in the standard and > > shall be supported by the MAC. > > Thanks for providing the full explanation, it would be good to have > that in the commit message. Okay thanks, I will provide the full explanation in the next commit message. > > The next question would be, is it just the NXP EQOS implementation > that this breaks on, or are other EQOS implementations affected? > > In other words, if we choose to conditionally enable the preable at > the PHY, should the generic parts of stmmac handle this rather than > ending up with multiple platform specific glue having to code this. > (This is something I really want to avoid - it doesn't scale.) >From the errata from NXP it sounds to me like it is a configuration issue by NXP. I checked the following ERRATAs from vendors where I have access to: - ST STM32MP1: not affected: https://www.st.com/resource/en/errata_sheet/es0438-stm32mp151x3x7x-device-errata-stmicroelectronics.pdf - Renesas RZN1: not affected: https://www.renesas.com/en/document/tcu/ethernet-mac-gmac-function-issue-0?r=1054561 - Starvive JH7110: not affected: https://doc-en.rvspace.org/JH7110/PDF/JH7110_Errata.pdf - NXP S32: affected: (ERR050706 under NDA) So from that I would conclude that it is an NXP specific issue and it's not the full EQOS implementation that is broken. Regards, Stefan