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charset=us-ascii Content-Disposition: inline In-Reply-To: <20251226225254.46197-2-21cnbao@gmail.com> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tangquan Zheng , Barry Song , Ryan Roberts , Leon Romanovsky , Anshuman Khandual , catalin.marinas@arm.com, linux-kernel@vger.kernel.org, Suren Baghdasaryan , iommu@lists.linux.dev, Marc Zyngier , xen-devel@lists.xenproject.org, robin.murphy@arm.com, Ard Biesheuvel , linux-arm-kernel@lists.infradead.org, m.szyprowski@samsung.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Dec 27, 2025 at 11:52:41AM +1300, Barry Song wrote: > From: Barry Song > > dcache_by_myline_op ensures completion of the data cache operations for a > region, while dcache_by_myline_op_nosync only issues them without waiting. > This enables deferred synchronization so completion for multiple regions > can be handled together later. > > Cc: Leon Romanovsky > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Marek Szyprowski > Cc: Robin Murphy > Cc: Ada Couprie Diaz > Cc: Ard Biesheuvel > Cc: Marc Zyngier > Cc: Anshuman Khandual > Cc: Ryan Roberts > Cc: Suren Baghdasaryan > Cc: Tangquan Zheng > Signed-off-by: Barry Song > --- > arch/arm64/include/asm/assembler.h | 24 +++++++++++++++++++----- > arch/arm64/kernel/relocate_kernel.S | 3 ++- > 2 files changed, 21 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h > index f0ca7196f6fa..b408ed61866f 100644 > --- a/arch/arm64/include/asm/assembler.h > +++ b/arch/arm64/include/asm/assembler.h > @@ -371,14 +371,13 @@ alternative_endif > * [start, end) with dcache line size explicitly provided. > * > * op: operation passed to dc instruction > - * domain: domain used in dsb instruction > * start: starting virtual address of the region > * end: end virtual address of the region > * linesz: dcache line size > * fixup: optional label to branch to on user fault > * Corrupts: start, end, tmp > */ > - .macro dcache_by_myline_op op, domain, start, end, linesz, tmp, fixup > + .macro raw_dcache_by_myline_op op, start, end, linesz, tmp, fixup > sub \tmp, \linesz, #1 > bic \start, \start, \tmp > .Ldcache_op\@: > @@ -402,14 +401,13 @@ alternative_endif > add \start, \start, \linesz > cmp \start, \end > b.lo .Ldcache_op\@ > - dsb \domain Naming nit, but I'd prefer this to be dcache_by_myline_op_nosync() for consistency with the other macros that you're adding. The 'raw' prefix is used by raw_dcache_line_size() to indicate that we're getting the value from the underlying hardware register. > > _cond_uaccess_extable .Ldcache_op\@, \fixup > .endm > > /* > * Macro to perform a data cache maintenance for the interval > - * [start, end) > + * [start, end) and wait for completion > * > * op: operation passed to dc instruction > * domain: domain used in dsb instruction > @@ -420,7 +418,23 @@ alternative_endif > */ > .macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup > dcache_line_size \tmp1, \tmp2 > - dcache_by_myline_op \op, \domain, \start, \end, \tmp1, \tmp2, \fixup > + raw_dcache_by_myline_op \op, \start, \end, \tmp1, \tmp2, \fixup > + dsb \domain > + .endm This could just be dcache_by_line_op_nosync() + dsb. Will