From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3C6BD46617 for ; Thu, 15 Jan 2026 19:09:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=sY5K62UAPSAhXYI6IjrBnXKn5tVWNnpg8VZkdg28VAo=; b=bJGPawbauyiP86pIbwXaaVsZ2L rZTj8lRklASNTA0dOw6S4O0EiY4kGYPSK9GTqqk07881JCd3n9TXiVbVmX6NtDVPeZ+O/1SD4Wxwc stWdu26Y4gFdqb1ZSys+E8ZZpYRmicuW9CawjTN9HpB694cjiRvkJaTE/lMOjMMg9uMFlqqi9Eymy 42EAGeloHiePIHojN9T3+xVWrZdnWZoyVFBjg5sATTeGjjpoYZ/2rYqzxNocuvIpTGavPOzuR1xPm TdrXyrYoxs5Qx/Y9LbR94dcoiMzyjnD0eN9aMBZSeVTpcrop/C0XMgEDr4ykir+HoTQ+X9mKCPN4w ybyf187g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vgSiL-0000000D1R0-42GO; Thu, 15 Jan 2026 19:09:01 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vgSiI-0000000D1Qe-11Qh for linux-arm-kernel@lists.infradead.org; Thu, 15 Jan 2026 19:09:00 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3BC101515; Thu, 15 Jan 2026 11:08:49 -0800 (PST) Received: from arm.com (arrakis.cambridge.arm.com [10.1.197.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 933E43F59E; Thu, 15 Jan 2026 11:08:50 -0800 (PST) Date: Thu, 15 Jan 2026 19:08:47 +0000 From: Catalin Marinas To: Ben Horgan Cc: amitsinght@marvell.com, baisheng.gao@unisoc.com, baolin.wang@linux.alibaba.com, carl@os.amperecomputing.com, dave.martin@arm.com, david@kernel.org, dfustini@baylibre.com, fenghuay@nvidia.com, gshan@redhat.com, james.morse@arm.com, jonathan.cameron@huawei.com, kobak@nvidia.com, lcherian@marvell.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, peternewman@google.com, punit.agrawal@oss.qualcomm.com, quic_jiles@quicinc.com, reinette.chatre@intel.com, rohit.mathew@arm.com, scott@os.amperecomputing.com, sdonthineni@nvidia.com, tan.shaopeng@fujitsu.com, xhao@linux.alibaba.com, will@kernel.org, corbet@lwn.net, maz@kernel.org, oupton@kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, kvmarm@lists.linux.dev Subject: Re: [PATCH v3 10/47] arm64: mpam: Initialise and context switch the MPAMSM_EL1 register Message-ID: References: <20260112165914.4086692-1-ben.horgan@arm.com> <20260112165914.4086692-11-ben.horgan@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260112165914.4086692-11-ben.horgan@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260115_110858_751365_69579DA0 X-CRM114-Status: GOOD ( 10.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jan 12, 2026 at 04:58:37PM +0000, Ben Horgan wrote: > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 0cdfb3728f43..2ede543b3eeb 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2491,6 +2491,8 @@ cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) > regval = READ_ONCE(per_cpu(arm64_mpam_current, cpu)); > > write_sysreg_s(regval, SYS_MPAM1_EL1); > + if (system_supports_sme()) > + write_sysreg_s(regval & (MPAMSM_EL1_PARTID_D | MPAMSM_EL1_PMG_D), SYS_MPAMSM_EL1); > isb(); Do we know for sure that system_supports_sme() returns true at this point (if SME supported)? Digging into the code, system_supports_sme() uses alternative_has_cap_unlikely() which relies on instruction patching. setup_system_capabilities(), IIUC, patches the alternatives after enable_cpu_capabilities(). I think you better use cpus_have_cap(). -- Catalin