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[35.187.245.222]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a802f97a81sm15301165ad.47.2026.01.23.01.53.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jan 2026 01:53:33 -0800 (PST) Date: Fri, 23 Jan 2026 09:53:28 +0000 From: Pranjal Shrivastava To: Nicolin Chen Cc: will@kernel.org, jean-philippe@linaro.org, robin.murphy@arm.com, joro@8bytes.org, jgg@nvidia.com, balbirs@nvidia.com, miko.lenczewski@arm.com, peterz@infradead.org, kevin.tian@intel.com, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v9 3/7] iommu/arm-smmu-v3: Introduce a per-domain arm_smmu_invs array Message-ID: References: <8c94c5194871ee1a0f3a6b49e18818b88f51226d.1766174731.git.nicolinc@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <8c94c5194871ee1a0f3a6b49e18818b88f51226d.1766174731.git.nicolinc@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260123_015335_521263_836EBB4F X-CRM114-Status: GOOD ( 17.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Dec 19, 2025 at 12:11:25PM -0800, Nicolin Chen wrote: > From: Jason Gunthorpe > > Create a new data structure to hold an array of invalidations that need to > be performed for the domain based on what masters are attached, to replace > the single smmu pointer and linked list of masters in the current design. > > Each array entry holds one of the invalidation actions - S1_ASID, S2_VMID, > ATS or their variant with information to feed invalidation commands to HW. > It is structured so that multiple SMMUs can participate in the same array, > removing one key limitation of the current system. > > To maximize performance, a sorted array is used as the data structure. It > allows grouping SYNCs together to parallelize invalidations. For instance, > it will group all the ATS entries after the ASID/VMID entry, so they will > all be pushed to the PCI devices in parallel with one SYNC. > > To minimize the locking cost on the invalidation fast path (reader of the > invalidation array), the array is managed with RCU. > > Provide a set of APIs to add/delete entries to/from an array, which cover > cannot-fail attach cases, e.g. attaching to arm_smmu_blocked_domain. Also > add kunit coverage for those APIs. > > Signed-off-by: Jason Gunthorpe > Reviewed-by: Jason Gunthorpe > Co-developed-by: Nicolin Chen > Signed-off-by: Nicolin Chen > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 98 +++++++ > .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 92 +++++++ > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 258 ++++++++++++++++++ > 3 files changed, 448 insertions(+) > Reviewed-by: Pranjal Shrivastava Thanks, Praan