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Tue, 27 Jan 2026 12:14:38 -0800 Date: Tue, 27 Jan 2026 12:14:37 -0800 From: Nicolin Chen To: Jason Gunthorpe CC: Pranjal Shrivastava , , , , , , , , , , , Subject: Re: [PATCH v9 6/7] iommu/arm-smmu-v3: Add arm_smmu_invs based arm_smmu_domain_inv_range() Message-ID: References: <06999367d001283744fd98eb7c1823afd516ce84.1766174731.git.nicolinc@nvidia.com> <20260127170837.GM1134360@nvidia.com> <20260127182348.GP1134360@nvidia.com> <20260127191938.GR1134360@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260127191938.GR1134360@nvidia.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB51:EE_|IA0PR12MB7532:EE_ X-MS-Office365-Filtering-Correlation-Id: d1309f51-4f16-4577-2bda-08de5de0bdd9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|1800799024|36860700013|3613699012; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2026 20:14:57.0503 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d1309f51-4f16-4577-2bda-08de5de0bdd9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB51.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7532 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260127_121501_928757_2521F846 X-CRM114-Status: GOOD ( 27.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jan 27, 2026 at 03:19:38PM -0400, Jason Gunthorpe wrote: > On Tue, Jan 27, 2026 at 10:37:44AM -0800, Nicolin Chen wrote: > > On Tue, Jan 27, 2026 at 02:23:48PM -0400, Jason Gunthorpe wrote: > > > On Tue, Jan 27, 2026 at 10:07:09AM -0800, Nicolin Chen wrote: > > > > > My understanding has been that this invalidation can run from an IRQ > > > > > context - we permit the use of the DMA API from an interrupt handler? > > > > > > > > > > I though that for rwsem the read side does not require the _irqsave, > > > > > even if it is in an irq context, unless the write side runs from an > > > > > IRQ. > > > > > > > > Hmm, is "rwsem" a typo? Because it's rwlock_t, which is spinlock :-/ > > > > > > Yeah, sorry > > > > > > > > Here the write side always runs from a process context. > > > > > > > > > > So the write side will block the IRQ which ensures we don't spin > > > > > during read in an IRQ. > > > > > > > > And, does write_lock_irqsave() disable global IRQ or local IRQ only? > > > > > > > > Documentation/locking/locktypes.rst mentions "local_irq_disable()".. > > > > > > It will only disable the local IRQ, since it is a spin type lock an IRQ on > > > another CPU can spin until it is unlocked. > > > > > > The main issue is if this CPU takes an IRQ while the write side is > > > locked and spins, then it will never unlock. > > > > Yea, that sounds unsafe. I'll send a v11 with read_lock_irqsave(). > > I'm explaining why it is safe now, the write side takes the irqsave so > the above can't happen. Sorry, I misunderstood.. > There is no case where the read side needs to block IRQ because if the > read side succeeds, an IRQ happens and tries to take another read > side, it will succeed not spin. Yea, I also went a bit deeper. It seems to depend on the CONFIG_QUEUED_RWLOCKS (ARM sets =y) 252 config QUEUED_RWLOCKS 253 def_bool y if ARCH_USE_QUEUED_RWLOCKS 254 depends on SMP && !PREEMPT_RT where a reader will not get blocked in our particular use case: 21 void __lockfunc queued_read_lock_slowpath(struct qrwlock *lock) 22 { 23 /* 24 * Readers come here when they cannot get the lock without waiting 25 */ 26 if (unlikely(in_interrupt())) { 27 /* 28 * Readers in interrupt context will get the lock immediately 29 * if the writer is just waiting (not holding the lock yet), 30 * so spin with ACQUIRE semantics until the lock is available 31 * without waiting in the queue. 32 */ 33 atomic_cond_read_acquire(&lock->cnts, !(VAL & _QW_LOCKED)); 34 return; And I don't see any non-hackable way for CONFIG_QUEUED_RWLOCKS=n unless CONFIG_PREEMPT_RT=y, which would be a different ball game that I assume SMMUv3 might not be completely compatible with. Thanks Nicolin