[PATCH 0/7] phy: rockchip: usbdp: Fixes, DP 1-lane support and cleanups

[PATCH 0/7] phy: rockchip: usbdp: Fixes, DP 1-lane support and cleanups

[Sebastian Reichel]

As there are some issues with the DisplayPort support, I went
though Rockchip's BSP kernel tree and looked for fixes. I found
two small changes for the initial register setup, which do not
help with the DP issue but seem sensible in general. Afterwards
I added one more fix, which corrects an issue that effectively
results in USB-C adapters with combined USB3+DP capabilities
not being able to use the DP part.

Afterwards I added one more patch adding single-lane DP support
(found in Rockchip BSP kernel) and a couple of cleanups from my
side. These are logically independent from the fixes, but I put
all together in a single series because they need to be applied
in the right order to avoid conflicts.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
Frank Wang (1):
      phy: rockchip: usbdp: Amend SSC modulation deviation

Sebastian Reichel (4):
      phy: rockchip: usbdp: Add missing mode_change update
      phy: rockchip: usbdp: Rename DP lane functions
      phy: rockchip: usbdp: Use FIELD_PREP_WM16_CONST
      phy: rockchip: usbdp: Cleanup DP lane selection function

William Wu (1):
      phy: rockchip: usbdp: Fix LFPS detect threshold control

Zhang Yubing (1):
      phy: rockchip: usbdp: Support single-lane DP

 drivers/phy/rockchip/phy-rockchip-usbdp.c | 114 +++++++++++++-----------------
 1 file changed, 48 insertions(+), 66 deletions(-)
---
base-commit: 18f7fcd5e69a04df57b563360b88be72471d6b62
change-id: 20260203-rockchip-usbdp-cleanup-5b59dfb561a3

Best regards,
-- 
Sebastian Reichel <sebastian.reichel@collabora.com>

[PATCH 1/7] phy: rockchip: usbdp: Amend SSC modulation deviation

[Sebastian Reichel]

From: Frank Wang <frank.wang@rock-chips.com>

Move SSC modulation deviation into private config of clock

 - 24M: 0x00d4[5:0] = 0x30
 - 26M: 0x00d4[5:0] = 0x33

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
[Taken over from rockchip's kernel tree; register 0x00d4 is not
described in the TRM]
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
 drivers/phy/rockchip/phy-rockchip-usbdp.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index fba35510d88c..b494819be284 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -350,7 +350,8 @@ static const struct reg_sequence rk_udphy_24m_refclk_cfg[] = {
 	{0x0a64, 0xa8}, {0x1a3c, 0xd0},
 	{0x1a44, 0xd0}, {0x1a48, 0x01},
 	{0x1a4c, 0x0d}, {0x1a54, 0xe0},
-	{0x1a5c, 0xe0}, {0x1a64, 0xa8}
+	{0x1a5c, 0xe0}, {0x1a64, 0xa8},
+	{0x00d4, 0x30}
 };
 
 static const struct reg_sequence rk_udphy_26m_refclk_cfg[] = {
@@ -377,7 +378,7 @@ static const struct reg_sequence rk_udphy_26m_refclk_cfg[] = {
 	{0x0c30, 0x0e}, {0x0c48, 0x06},
 	{0x1c30, 0x0e}, {0x1c48, 0x06},
 	{0x028c, 0x18}, {0x0af0, 0x00},
-	{0x1af0, 0x00}
+	{0x1af0, 0x00}, {0x00d4, 0x33}
 };
 
 static const struct reg_sequence rk_udphy_init_sequence[] = {
@@ -412,8 +413,7 @@ static const struct reg_sequence rk_udphy_init_sequence[] = {
 	{0x0070, 0x7d}, {0x0074, 0x68},
 	{0x0af4, 0x1a}, {0x1af4, 0x1a},
 	{0x0440, 0x3f}, {0x10d4, 0x08},
-	{0x20d4, 0x08}, {0x00d4, 0x30},
-	{0x0024, 0x6e},
+	{0x20d4, 0x08}, {0x0024, 0x6e}
 };
 
 static inline int rk_udphy_grfreg_write(struct regmap *base,

-- 
2.51.0

[PATCH 2/7] phy: rockchip: usbdp: Fix LFPS detect threshold control

[Sebastian Reichel]

From: William Wu <william.wu@rock-chips.com>

According to the LFPS Tx Low Power/LFPS Rx Detect Threshold [1],
the device under test(DUT) must not respond if LFPS below the
minimum LFPS Rx Detect Threshold 100mV. Test fail on Rockchip
platforms, because the default LFPS detect threshold is set to
65mV.

The USBDP PHY LFPS detect threshold voltage could be set to
30mV ~ 140mV, and since there could be 10-20% PVT variation,
we set LFPS detect threshold voltage to 110mV.

[1] https://compliance.usb.org/resources/LFPS_Rx_Tx_Low_Power_Compliance_Update_Rev5.pdf

Signed-off-by: William Wu <william.wu@rock-chips.com>
[Taken over from rockchip's kernel tree; the registers are not described
in the TRM]
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
 drivers/phy/rockchip/phy-rockchip-usbdp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index b494819be284..7e4142aef192 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -413,7 +413,8 @@ static const struct reg_sequence rk_udphy_init_sequence[] = {
 	{0x0070, 0x7d}, {0x0074, 0x68},
 	{0x0af4, 0x1a}, {0x1af4, 0x1a},
 	{0x0440, 0x3f}, {0x10d4, 0x08},
-	{0x20d4, 0x08}, {0x0024, 0x6e}
+	{0x20d4, 0x08}, {0x0024, 0x6e},
+	{0x09c0, 0x0a}, {0x19c0, 0x0a}
 };
 
 static inline int rk_udphy_grfreg_write(struct regmap *base,

-- 
2.51.0

[PATCH 3/7] phy: rockchip: usbdp: Add missing mode_change update

[Sebastian Reichel]

rk_udphy_set_typec_default_mapping() updates the available modes,
but does not set the mode_change as required. This results in
missing re-initialization and thus non-working DisplayPort.

Fix this issue by introducing a new helper to update the available
modes.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
 drivers/phy/rockchip/phy-rockchip-usbdp.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 7e4142aef192..5304e2d86d11 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -619,6 +619,15 @@ static void rk_udphy_dp_hpd_event_trigger(struct rk_udphy *udphy, bool hpd)
 	rk_udphy_grfreg_write(udphy->vogrf, &cfg->vogrfcfg[udphy->id].hpd_trigger, hpd);
 }
 
+static void rk_udphy_mode_set(struct rk_udphy *udphy, u8 mode)
+{
+	if (udphy->mode == mode)
+		return;
+
+	udphy->mode_change = true;
+	udphy->mode = mode;
+}
+
 static void rk_udphy_set_typec_default_mapping(struct rk_udphy *udphy)
 {
 	if (udphy->flip) {
@@ -649,7 +658,7 @@ static void rk_udphy_set_typec_default_mapping(struct rk_udphy *udphy)
 		gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 1);
 	}
 
-	udphy->mode = UDPHY_MODE_DP_USB;
+	rk_udphy_mode_set(udphy, UDPHY_MODE_DP_USB);
 }
 
 static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw,
@@ -1387,10 +1396,7 @@ static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux,
 			usleep_range(750, 800);
 			rk_udphy_dp_hpd_event_trigger(udphy, true);
 		} else if (data->status & DP_STATUS_HPD_STATE) {
-			if (udphy->mode != mode) {
-				udphy->mode = mode;
-				udphy->mode_change = true;
-			}
+			rk_udphy_mode_set(udphy, mode);
 			rk_udphy_dp_hpd_event_trigger(udphy, true);
 		} else {
 			rk_udphy_dp_hpd_event_trigger(udphy, false);

-- 
2.51.0

[PATCH 4/7] phy: rockchip: usbdp: Support single-lane DP

[Sebastian Reichel]

From: Zhang Yubing <yubing.zhang@rock-chips.com>

Implement support for using just a single DisplayPort line.

Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
 drivers/phy/rockchip/phy-rockchip-usbdp.c | 61 +++++++++++++------------------
 1 file changed, 25 insertions(+), 36 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 5304e2d86d11..29cf3f3bcec4 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -193,6 +193,7 @@ struct rk_udphy {
 	int id;
 
 	bool dp_in_use;
+	int dp_lanes;
 
 	/* PHY const config */
 	const struct rk_udphy_cfg *cfgs;
@@ -537,6 +538,13 @@ static void rk_udphy_usb_bvalid_enable(struct rk_udphy *udphy, u8 enable)
  * <0 1>                  dpln0         dpln1       usbrx         usbtx
  * <2 3>                  usbrx         usbtx       dpln0         dpln1
  * ---------------------------------------------------------------------------
+ * if 1 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x>;
+ * sample as follow:
+ * ---------------------------------------------------------------------------
+ *                        B11-B10       A2-A3       A11-A10       B2-B3
+ * rockchip,dp-lane-mux   ln0(tx/rx)    ln1(tx)     ln2(tx/rx)    ln3(tx)
+ * <0>                    dpln0         \           usbrx         usbtx
+ * ---------------------------------------------------------------------------
  */
 
 static void rk_udphy_dplane_select(struct rk_udphy *udphy)
@@ -544,18 +552,18 @@ static void rk_udphy_dplane_select(struct rk_udphy *udphy)
 	const struct rk_udphy_cfg *cfg = udphy->cfgs;
 	u32 value = 0;
 
-	switch (udphy->mode) {
-	case UDPHY_MODE_DP:
-		value |= 2 << udphy->dp_lane_sel[2] * 2;
+	switch (udphy->dp_lanes) {
+	case 4:
 		value |= 3 << udphy->dp_lane_sel[3] * 2;
+		value |= 2 << udphy->dp_lane_sel[2] * 2;
 		fallthrough;
 
-	case UDPHY_MODE_DP_USB:
-		value |= 0 << udphy->dp_lane_sel[0] * 2;
+	case 2:
 		value |= 1 << udphy->dp_lane_sel[1] * 2;
-		break;
+		fallthrough;
 
-	case UDPHY_MODE_USB:
+	case 1:
+		value |= 0 << udphy->dp_lane_sel[0] * 2;
 		break;
 
 	default:
@@ -568,28 +576,6 @@ static void rk_udphy_dplane_select(struct rk_udphy *udphy)
 		     FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value);
 }
 
-static int rk_udphy_dplane_get(struct rk_udphy *udphy)
-{
-	int dp_lanes;
-
-	switch (udphy->mode) {
-	case UDPHY_MODE_DP:
-		dp_lanes = 4;
-		break;
-
-	case UDPHY_MODE_DP_USB:
-		dp_lanes = 2;
-		break;
-
-	case UDPHY_MODE_USB:
-	default:
-		dp_lanes = 0;
-		break;
-	}
-
-	return dp_lanes;
-}
-
 static void rk_udphy_dplane_enable(struct rk_udphy *udphy, int dp_lanes)
 {
 	u32 val = 0;
@@ -659,6 +645,7 @@ static void rk_udphy_set_typec_default_mapping(struct rk_udphy *udphy)
 	}
 
 	rk_udphy_mode_set(udphy, UDPHY_MODE_DP_USB);
+	udphy->dp_lanes = 2;
 }
 
 static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw,
@@ -897,7 +884,7 @@ static int rk_udphy_parse_lane_mux_data(struct rk_udphy *udphy)
 		return 0;
 	}
 
-	if (num_lanes != 2 && num_lanes != 4)
+	if (num_lanes != 1 && num_lanes != 2 && num_lanes != 4)
 		return dev_err_probe(udphy->dev, -EINVAL,
 				     "invalid number of lane mux\n");
 
@@ -923,7 +910,8 @@ static int rk_udphy_parse_lane_mux_data(struct rk_udphy *udphy)
 	}
 
 	udphy->mode = UDPHY_MODE_DP;
-	if (num_lanes == 2) {
+	udphy->dp_lanes = num_lanes;
+	if (num_lanes == 1 || num_lanes == 2) {
 		udphy->mode |= UDPHY_MODE_USB;
 		udphy->flip = (udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP);
 	}
@@ -1076,18 +1064,17 @@ static int rk_udphy_dp_phy_exit(struct phy *phy)
 static int rk_udphy_dp_phy_power_on(struct phy *phy)
 {
 	struct rk_udphy *udphy = phy_get_drvdata(phy);
-	int ret, dp_lanes;
+	int ret;
 
 	mutex_lock(&udphy->mutex);
 
-	dp_lanes = rk_udphy_dplane_get(udphy);
-	phy_set_bus_width(phy, dp_lanes);
+	phy_set_bus_width(phy, udphy->dp_lanes);
 
 	ret = rk_udphy_power_on(udphy, UDPHY_MODE_DP);
 	if (ret)
 		goto unlock;
 
-	rk_udphy_dplane_enable(udphy, dp_lanes);
+	rk_udphy_dplane_enable(udphy, udphy->dp_lanes);
 
 	rk_udphy_dplane_select(udphy);
 
@@ -1367,6 +1354,7 @@ static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux,
 		udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
 		udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
 		mode = UDPHY_MODE_DP;
+		udphy->dp_lanes = 4;
 		break;
 
 	case TYPEC_DP_STATE_D:
@@ -1383,6 +1371,7 @@ static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux,
 			udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
 		}
 		mode = UDPHY_MODE_DP_USB;
+		udphy->dp_lanes = 2;
 		break;
 	}
 
@@ -1531,7 +1520,7 @@ static int rk_udphy_probe(struct platform_device *pdev)
 		ret = PTR_ERR(udphy->phy_dp);
 		return dev_err_probe(dev, ret, "failed to create DP phy\n");
 	}
-	phy_set_bus_width(udphy->phy_dp, rk_udphy_dplane_get(udphy));
+	phy_set_bus_width(udphy->phy_dp, udphy->dp_lanes);
 	udphy->phy_dp->attrs.max_link_rate = 8100;
 	phy_set_drvdata(udphy->phy_dp, udphy);
 

-- 
2.51.0

[PATCH 5/7] phy: rockchip: usbdp: Rename DP lane functions

[Sebastian Reichel]

The common prefix for DisplayPort related functions is rk_udphy_dp_
(with a final _), so update the two DP lane functions to follow that
scheme.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
 drivers/phy/rockchip/phy-rockchip-usbdp.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 29cf3f3bcec4..4388105dd8ce 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -547,7 +547,7 @@ static void rk_udphy_usb_bvalid_enable(struct rk_udphy *udphy, u8 enable)
  * ---------------------------------------------------------------------------
  */
 
-static void rk_udphy_dplane_select(struct rk_udphy *udphy)
+static void rk_udphy_dp_lane_select(struct rk_udphy *udphy)
 {
 	const struct rk_udphy_cfg *cfg = udphy->cfgs;
 	u32 value = 0;
@@ -576,7 +576,7 @@ static void rk_udphy_dplane_select(struct rk_udphy *udphy)
 		     FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value);
 }
 
-static void rk_udphy_dplane_enable(struct rk_udphy *udphy, int dp_lanes)
+static void rk_udphy_dp_lane_enable(struct rk_udphy *udphy, int dp_lanes)
 {
 	u32 val = 0;
 	int i;
@@ -1074,9 +1074,9 @@ static int rk_udphy_dp_phy_power_on(struct phy *phy)
 	if (ret)
 		goto unlock;
 
-	rk_udphy_dplane_enable(udphy, udphy->dp_lanes);
+	rk_udphy_dp_lane_enable(udphy, udphy->dp_lanes);
 
-	rk_udphy_dplane_select(udphy);
+	rk_udphy_dp_lane_select(udphy);
 
 unlock:
 	mutex_unlock(&udphy->mutex);
@@ -1094,7 +1094,7 @@ static int rk_udphy_dp_phy_power_off(struct phy *phy)
 	struct rk_udphy *udphy = phy_get_drvdata(phy);
 
 	mutex_lock(&udphy->mutex);
-	rk_udphy_dplane_enable(udphy, 0);
+	rk_udphy_dp_lane_enable(udphy, 0);
 	rk_udphy_power_off(udphy, UDPHY_MODE_DP);
 	mutex_unlock(&udphy->mutex);
 

-- 
2.51.0

[PATCH 6/7] phy: rockchip: usbdp: Use FIELD_PREP_WM16_CONST

[Sebastian Reichel]

Cleanup code by replacing open-coded version of FIELD_PREP_WM16_CONST
with the existing helper macro.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
 drivers/phy/rockchip/phy-rockchip-usbdp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 4388105dd8ce..9291f56120f1 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -12,6 +12,7 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/hw_bitfield.h>
 #include <linux/mfd/syscon.h>
 #include <linux/mod_devicetable.h>
 #include <linux/module.h>
@@ -75,7 +76,6 @@
 #define TRSV_LN2_MON_RX_CDR_DONE_OFFSET		0x1b84	/* trsv_reg06E1 */
 #define TRSV_LN2_MON_RX_CDR_LOCK_DONE		BIT(0)
 
-#define BIT_WRITEABLE_SHIFT			16
 #define PHY_AUX_DP_DATA_POL_NORMAL		0
 #define PHY_AUX_DP_DATA_POL_INVERT		1
 #define PHY_LANE_MUX_USB			0
@@ -104,8 +104,8 @@ struct rk_udphy_grf_reg {
 #define _RK_UDPHY_GEN_GRF_REG(offset, mask, disable, enable) \
 {\
 	offset, \
-	FIELD_PREP_CONST(mask, disable) | (mask << BIT_WRITEABLE_SHIFT), \
-	FIELD_PREP_CONST(mask, enable) | (mask << BIT_WRITEABLE_SHIFT), \
+	FIELD_PREP_WM16_CONST(mask, disable), \
+	FIELD_PREP_WM16_CONST(mask, enable), \
 }
 
 #define RK_UDPHY_GEN_GRF_REG(offset, bitend, bitstart, disable, enable) \

-- 
2.51.0

[PATCH 7/7] phy: rockchip: usbdp: Cleanup DP lane selection function

[Sebastian Reichel]

Use FIELD_PREP_WM16() helpers to simplify the DP lane selection
logic.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
 drivers/phy/rockchip/phy-rockchip-usbdp.c | 28 +++++++---------------------
 1 file changed, 7 insertions(+), 21 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 9291f56120f1..ebc11d06e5ea 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -550,30 +550,16 @@ static void rk_udphy_usb_bvalid_enable(struct rk_udphy *udphy, u8 enable)
 static void rk_udphy_dp_lane_select(struct rk_udphy *udphy)
 {
 	const struct rk_udphy_cfg *cfg = udphy->cfgs;
-	u32 value = 0;
-
-	switch (udphy->dp_lanes) {
-	case 4:
-		value |= 3 << udphy->dp_lane_sel[3] * 2;
-		value |= 2 << udphy->dp_lane_sel[2] * 2;
-		fallthrough;
-
-	case 2:
-		value |= 1 << udphy->dp_lane_sel[1] * 2;
-		fallthrough;
+	u32 value = FIELD_PREP_WM16(DP_LANE_SEL_ALL, 0);
+	int i;
 
-	case 1:
-		value |= 0 << udphy->dp_lane_sel[0] * 2;
-		break;
+	for (i = 0; i < udphy->dp_lanes; i++)
+		value |= field_prep(DP_LANE_SEL_N(udphy->dp_lane_sel[i]), i);
 
-	default:
-		break;
-	}
+	value |= FIELD_PREP_WM16(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel);
+	value |= FIELD_PREP_WM16(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel);
 
-	regmap_write(udphy->vogrf, cfg->vogrfcfg[udphy->id].dp_lane_reg,
-		     ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) |
-		     FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) |
-		     FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value);
+	regmap_write(udphy->vogrf, cfg->vogrfcfg[udphy->id].dp_lane_reg, value);
 }
 
 static void rk_udphy_dp_lane_enable(struct rk_udphy *udphy, int dp_lanes)

-- 
2.51.0

Re:[PATCH 0/7] phy: rockchip: usbdp: Fixes, DP 1-lane support and cleanups

[Andy Yan]

Hello Sebastian，


At 2026-02-04 02:41:26, "Sebastian Reichel" <sebastian.reichel@collabora.com> wrote:
>As there are some issues with the DisplayPort support, I went
>though Rockchip's BSP kernel tree and looked for fixes. I found
>two small changes for the initial register setup, which do not
>help with the DP issue but seem sensible in general. Afterwards
>I added one more fix, which corrects an issue that effectively
>results in USB-C adapters with combined USB3+DP capabilities
>not being able to use the DP part.
>
>Afterwards I added one more patch adding single-lane DP support
>(found in Rockchip BSP kernel) and a couple of cleanups from my
>side. These are logically independent from the fixes, but I put
>all together in a single series because they need to be applied
>in the right order to avoid conflicts.
>
>Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
>---
>Frank Wang (1):
>      phy: rockchip: usbdp: Amend SSC modulation deviation
>
>Sebastian Reichel (4):
>      phy: rockchip: usbdp: Add missing mode_change update
>      phy: rockchip: usbdp: Rename DP lane functions
>      phy: rockchip: usbdp: Use FIELD_PREP_WM16_CONST
>      phy: rockchip: usbdp: Cleanup DP lane selection function
>
>William Wu (1):
>      phy: rockchip: usbdp: Fix LFPS detect threshold control
>
>Zhang Yubing (1):
>      phy: rockchip: usbdp: Support single-lane DP
>
> drivers/phy/rockchip/phy-rockchip-usbdp.c | 114 +++++++++++++-----------------
> 1 file changed, 48 insertions(+), 66 deletions(-)



After applying this series of patches, the hub that previously couldn’t recognize Alt Mode can now detect it and work properly, 
but it also triggers a USB-related SERR — did I miss something？


[    2.639842][  T244] 8021q: adding VLAN 0 to HW filter on device eth1
[    3.872936][   T23] usb 3-1: new high-speed USB device number 2 using xhci-hcd
[    4.011232][   T23] usb 3-1: New USB device found, idVendor=2109, idProduct=2817, bcdDevice= 5.54
[    4.012102][   T23] usb 3-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[    4.012908][   T23] usb 3-1: Product: USB2.0 Hub             
[    4.013469][   T23] usb 3-1: Manufacturer: VIA Labs, Inc.         
[    4.014064][   T23] usb 3-1: SerialNumber: 000000000
[    4.071154][   T23] hub 3-1:1.0: USB hub found
[    4.071876][   T23] hub 3-1:1.0: 5 ports detected
[    4.385554][    C1] SError Interrupt on CPU1, code 0x00000000bf000002 -- SError
[    4.385592][    C1] CPU: 1 UID: 0 PID: 96 Comm: kworker/1:1 Tainted: G   M                6.19.0-rc4+ #223 PREEMPT 
[    4.385623][    C1] Tainted: [M]=MACHINE_CHECK
[    4.385632][    C1] Hardware name: ArmSoM Sige5 (DT)
[    4.385644][    C1] Workqueue: usb_hub_wq hub_event
[    4.385680][    C1] pstate: 000000c5 (nzcv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[    4.385701][    C1] pc : el1_abort+0x34/0x68
[    4.385728][    C1] lr : el1_abort+0x24/0x68
[    4.385749][    C1] sp : ffff8000833a36c0
[    4.385758][    C1] x29: ffff8000833a36c0 x28: ffff0000c3568000 x27: ffff0000c3d70c48
[    4.385792][    C1] x26: ffff0000c13c8d78 x25: 0000000000000004 x24: 0000000000000001
[    4.385823][    C1] x23: 00000000600000c5 x22: ffff800084088430 x21: 0000000096000210
[    4.385854][    C1] x20: 0000000000000000 x19: ffff8000833a3700 x18: 00000000ffffffff
[    4.385885][    C1] x17: ffff800083179000 x16: ffffffffffffffff x15: ffff0000c11ba128
[    4.385916][    C1] x14: 0000000000000376 x13: 0000000000000376 x12: 0000000000000000
[    4.385946][    C1] x11: 00000000000000c0 x10: 0000000000000af0 x9 : 0000000000002303
[    4.385976][    C1] x8 : ffff8000833a3740 x7 : ffff8000833a3830 x6 : ffff8000833a3800
[    4.386006][    C1] x5 : ffff8000833a3780 x4 : ffff8000833a4000 x3 : ffff8000812c986c
[    4.386037][    C1] x2 : ffff8000812c986c x1 : 00000000000000c0 x0 : 0000000000000000
[    4.386071][    C1] Kernel panic - not syncing: Asynchronous SError Interrupt
[    4.386085][    C1] CPU: 1 UID: 0 PID: 96 Comm: kworker/1:1 Tainted: G   M                6.19.0-rc4+ #223 PREEMPT 
[    4.386113][    C1] Tainted: [M]=MACHINE_CHECK
[    4.386121][    C1] Hardware name: ArmSoM Sige5 (DT)
[    4.386131][    C1] Workqueue: usb_hub_wq hub_event
[    4.386156][    C1] Call trace:
[    4.386164][    C1]  show_stack+0x18/0x24 (C)
[    4.386202][    C1]  dump_stack_lvl+0x60/0x80
[    4.386236][    C1]  dump_stack+0x18/0x24
[    4.386266][    C1]  vpanic+0xf8/0x2ac
[    4.386290][    C1]  trace_suspend_resume+0x0/0x7c
[    4.386314][    C1]  add_taint+0x0/0xbc
[    4.386342][    C1]  arm64_serror_panic+0x70/0x80
[    4.386364][    C1]  do_serror+0x3c/0x74
[    4.386384][    C1]  el1h_64_error_handler+0x34/0x50
[    4.386414][    C1]  el1h_64_error+0x6c/0x70
[    4.386436][    C1]  el1_abort+0x34/0x68 (P)
[    4.386462][    C1]  el1h_64_sync_handler+0x50/0xac
[    4.386490][    C1]  el1h_64_sync+0x6c/0x70
[    4.386511][    C1]  xhci_portsc_readl+0x4/0x1c (P)
[    4.386538][    C1]  usb_hcd_submit_urb+0x48c/0xa3c
[    4.386565][    C1]  usb_submit_urb+0x1e0/0x650
[    4.386593][    C1]  usb_start_wait_urb+0x74/0x17c
[    4.386621][    C1]  usb_control_msg+0xc4/0x140
[    4.386648][    C1]  hub_port_reset+0x118/0x9c0
[    4.386672][    C1]  hub_port_init+0xb4/0xd84
[    4.386694][    C1]  hub_event+0x10e4/0x1a5c
[    4.386718][    C1]  process_one_work+0x16c/0x3d4
[    4.386752][    C1]  worker_thread+0x2c4/0x3f4
[    4.386773][    C1]  kthread+0x130/0x1ec
[    4.386803][    C1]  ret_from_fork+0x10/0x20
[    4.386829][    C1] SMP: stopping secondary CPUs
[    4.386854][    C1] Kernel Offset: disabled
[    4.386861][    C1] CPU features: 0x200000,10410001,00008000,0400420b
[    4.386876][    C1] Memory Limit: none
[    4.414238][    C1] ---[ end Kernel panic - not syncing: Asynchronous SError Interrupt ]---


>---
>base-commit: 18f7fcd5e69a04df57b563360b88be72471d6b62
>change-id: 20260203-rockchip-usbdp-cleanup-5b59dfb561a3
>
>Best regards,
>-- 
>Sebastian Reichel <sebastian.reichel@collabora.com>
>
>
>_______________________________________________
>Linux-rockchip mailing list
>Linux-rockchip@lists.infradead.org
>http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: [PATCH 0/7] phy: rockchip: usbdp: Fixes, DP 1-lane support and cleanups

[Sebastian Reichel]

[-- Attachment #1: Type: text/plain, Size: 2208 bytes --]

Hi,

On Wed, Feb 04, 2026 at 08:09:22PM +0800, Andy Yan wrote:
> Hello Sebastian，
> 
> At 2026-02-04 02:41:26, "Sebastian Reichel" <sebastian.reichel@collabora.com> wrote:
> >As there are some issues with the DisplayPort support, I went
> >though Rockchip's BSP kernel tree and looked for fixes. I found
> >two small changes for the initial register setup, which do not
> >help with the DP issue but seem sensible in general. Afterwards
> >I added one more fix, which corrects an issue that effectively
> >results in USB-C adapters with combined USB3+DP capabilities
> >not being able to use the DP part.
> >
> >Afterwards I added one more patch adding single-lane DP support
> >(found in Rockchip BSP kernel) and a couple of cleanups from my
> >side. These are logically independent from the fixes, but I put
> >all together in a single series because they need to be applied
> >in the right order to avoid conflicts.
> >
> >Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> >---
> >Frank Wang (1):
> >      phy: rockchip: usbdp: Amend SSC modulation deviation
> >
> >Sebastian Reichel (4):
> >      phy: rockchip: usbdp: Add missing mode_change update
> >      phy: rockchip: usbdp: Rename DP lane functions
> >      phy: rockchip: usbdp: Use FIELD_PREP_WM16_CONST
> >      phy: rockchip: usbdp: Cleanup DP lane selection function
> >
> >William Wu (1):
> >      phy: rockchip: usbdp: Fix LFPS detect threshold control
> >
> >Zhang Yubing (1):
> >      phy: rockchip: usbdp: Support single-lane DP
> >
> > drivers/phy/rockchip/phy-rockchip-usbdp.c | 114 +++++++++++++-----------------
> > 1 file changed, 48 insertions(+), 66 deletions(-)
> 
> After applying this series of patches, the hub that previously
> couldn’t recognize Alt Mode can now detect it and work properly,
> but it also triggers a USB-related SERR — did I miss something？

I thought this was from a different patch that I needed to get DP
working. I've spent the last week debugging this and I'm just about
to send v2 with a workaround. FWIW the SError is not introduced by
this series, but before it was much harder to run into it.

Greetings,

-- Sebastian

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]