From: Niklas Cassel <cassel@kernel.org>
To: Koichiro Den <den@valinux.co.jp>
Cc: jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org,
kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com,
heiko@sntech.de, kishon@kernel.org, jdmason@kudzu.us,
dave.jiang@intel.com, allenbh@gmail.com,
shawn.lin@rock-chips.com, Frank.Li@nxp.com,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, ntb@lists.linux.dev
Subject: Re: [PATCH v7 5/9] PCI: dwc: ep: Expose integrated eDMA resources via EPC aux-resource API
Date: Mon, 16 Feb 2026 15:12:53 +0100 [thread overview]
Message-ID: <aZMl5SVsF_mzEsNT@ryzen> (raw)
In-Reply-To: <20260215163847.3522572-6-den@valinux.co.jp>
On Mon, Feb 16, 2026 at 01:38:43AM +0900, Koichiro Den wrote:
> Implement the EPC aux-resource API for DesignWare endpoint controllers
> with integrated eDMA.
>
> Report:
> - DMA controller MMIO window (PCI_EPC_AUX_DMA_CTRL_MMIO)
> - interrupt-emulation doorbell register (PCI_EPC_AUX_DOORBELL_MMIO),
> including its Linux IRQ
> - per-channel LL descriptor regions (PCI_EPC_AUX_DMA_CHAN_DESC)
>
> If the DMA controller MMIO window is already exposed via a
> platform-owned fixed BAR subregion, also provide the BAR number and
> offset so EPF drivers can reuse it without reprogramming the BAR.
>
> Signed-off-by: Koichiro Den <den@valinux.co.jp>
> ---
> .../pci/controller/dwc/pcie-designware-ep.c | 149 ++++++++++++++++++
> 1 file changed, 149 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 7e7844ff0f7e..ffd2797b7b81 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -808,6 +808,154 @@ dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
> return ep->ops->get_features(ep);
> }
>
> +static const struct pci_epc_bar_rsvd_region *
> +dw_pcie_ep_find_bar_rsvd_region(struct dw_pcie_ep *ep,
> + enum pci_epc_bar_rsvd_region_type type,
> + enum pci_barno *bar,
> + resource_size_t *bar_offset)
> +{
> + const struct pci_epc_features *features;
> + const struct pci_epc_bar_desc *bar_desc;
> + const struct pci_epc_bar_rsvd_region *r;
> + int i, j;
> +
> + if (!ep->ops->get_features)
> + return NULL;
> +
> + features = ep->ops->get_features(ep);
> + if (!features)
> + return NULL;
> +
> + for (i = BAR_0; i <= BAR_5; i++) {
> + bar_desc = &features->bar[i];
> +
> + if (!bar_desc->nr_rsvd_regions || !bar_desc->rsvd_regions)
> + continue;
> +
> + for (j = 0; j < bar_desc->nr_rsvd_regions; j++) {
> + r = &bar_desc->rsvd_regions[j];
> +
> + if (r->type != type)
> + continue;
> +
> + if (bar)
> + *bar = i;
> + if (bar_offset)
> + *bar_offset = r->offset;
> + return r;
> + }
> + }
> +
> + return NULL;
> +}
> +
> +static int
> +dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> + struct pci_epc_aux_resource *resources,
> + int num_resources)
> +{
> + struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + const struct pci_epc_bar_rsvd_region *rsvd;
> + struct dw_edma_chip *edma = &pci->edma;
> + enum pci_barno dma_ctrl_bar = NO_BAR;
> + int ll_cnt = 0, needed, idx = 0;
> + resource_size_t db_offset = edma->db_offset;
> + resource_size_t dma_ctrl_bar_offset = 0;
> + resource_size_t dma_reg_size;
> + unsigned int i;
> +
> + if (!pci->edma_reg_size)
> + return 0;
> +
> + dma_reg_size = pci->edma_reg_size;
> +
> + for (i = 0; i < edma->ll_wr_cnt; i++)
> + if (edma->ll_region_wr[i].sz)
> + ll_cnt++;
> +
> + for (i = 0; i < edma->ll_rd_cnt; i++)
> + if (edma->ll_region_rd[i].sz)
> + ll_cnt++;
> +
> + needed = 1 + ll_cnt + (db_offset != ~0 ? 1 : 0);
> +
> + /* Count query mode */
> + if (!resources || !num_resources)
> + return needed;
> +
> + if (num_resources < needed)
> + return -ENOSPC;
> +
> + rsvd = dw_pcie_ep_find_bar_rsvd_region(ep,
> + PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO,
> + &dma_ctrl_bar,
> + &dma_ctrl_bar_offset);
> + if (rsvd && rsvd->size < dma_reg_size)
> + dma_reg_size = rsvd->size;
> +
> + /* DMA register block */
> + resources[idx++] = (struct pci_epc_aux_resource) {
> + .type = PCI_EPC_AUX_DMA_CTRL_MMIO,
> + .phys_addr = pci->edma_reg_phys,
> + .size = dma_reg_size,
> + .bar = dma_ctrl_bar,
> + .bar_offset = dma_ctrl_bar_offset,
> + };
> +
> + /*
> + * For interrupt-emulation doorbells, report a standalone resource
> + * instead of bundling it into the DMA controller MMIO resource.
> + */
> + if (db_offset != ~0) {
> + if (dma_reg_size < sizeof(u32) ||
> + db_offset > dma_reg_size - sizeof(u32))
In your other patch, you used:
if (size_add(offset, sizeof(u32)) > epf->bar[bar].size)
For consistency, do you perhaps want to use the same here?
size_add(db_offset, sizeof(u32)) > dma_reg_size ?
Kind regards,
Niklas
next prev parent reply other threads:[~2026-02-16 14:13 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-15 16:38 [PATCH v7 0/9] PCI: endpoint: pci-ep-msi: Add embedded doorbell fallback Koichiro Den
2026-02-15 16:38 ` [PATCH v7 1/9] PCI: endpoint: Describe reserved subregions within BARs Koichiro Den
2026-02-15 16:38 ` [PATCH v7 2/9] PCI: dw-rockchip: Describe RK3588 BAR4 DMA ctrl window Koichiro Den
2026-02-15 16:38 ` [PATCH v7 3/9] PCI: endpoint: Add auxiliary resource query API Koichiro Den
2026-02-16 15:56 ` Frank Li
2026-02-15 16:38 ` [PATCH v7 4/9] PCI: dwc: Record integrated eDMA register window Koichiro Den
2026-02-15 16:38 ` [PATCH v7 5/9] PCI: dwc: ep: Expose integrated eDMA resources via EPC aux-resource API Koichiro Den
2026-02-16 14:12 ` Niklas Cassel [this message]
2026-02-16 15:06 ` Koichiro Den
2026-02-16 16:02 ` Frank Li
2026-02-15 16:38 ` [PATCH v7 6/9] PCI: endpoint: pci-ep-msi: Refactor doorbell allocation for new backends Koichiro Den
2026-02-16 16:07 ` Frank Li
2026-02-15 16:38 ` [PATCH v7 7/9] PCI: endpoint: pci-epf-vntb: Reuse pre-exposed doorbells and IRQ flags Koichiro Den
2026-02-16 16:14 ` Frank Li
2026-02-17 1:39 ` Koichiro Den
2026-02-15 16:38 ` [PATCH v7 8/9] PCI: endpoint: pci-epf-test: Reuse pre-exposed doorbell targets Koichiro Den
2026-02-16 16:18 ` Frank Li
2026-02-15 16:38 ` [PATCH v7 9/9] PCI: endpoint: pci-ep-msi: Add embedded eDMA doorbell fallback Koichiro Den
2026-02-16 16:24 ` Frank Li
2026-02-17 1:42 ` Koichiro Den
2026-02-17 4:00 ` Koichiro Den
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=aZMl5SVsF_mzEsNT@ryzen \
--to=cassel@kernel.org \
--cc=Frank.Li@nxp.com \
--cc=allenbh@gmail.com \
--cc=bhelgaas@google.com \
--cc=dave.jiang@intel.com \
--cc=den@valinux.co.jp \
--cc=heiko@sntech.de \
--cc=jdmason@kudzu.us \
--cc=jingoohan1@gmail.com \
--cc=kishon@kernel.org \
--cc=kwilczynski@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-rockchip@lists.infradead.org \
--cc=lpieralisi@kernel.org \
--cc=mani@kernel.org \
--cc=ntb@lists.linux.dev \
--cc=robh@kernel.org \
--cc=shawn.lin@rock-chips.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox